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Add ldrd and strd instructions and tests (#348)

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* LDRD and STRD implementation and tests
This commit is contained in:
Garret Reece
2017-06-26 17:22:59 -05:00
committed by GitHub
parent 520a9be47d
commit e931992abb
2 changed files with 61 additions and 0 deletions
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tests/test_armv7cpu.py
+31
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@@ -764,6 +764,16 @@ class Armv7CpuInstructions(unittest.TestCase):
self.assertEqual(self.rf.read('R1'), 42)
self.assertEqual(self.rf.read('SP'), pre_stack - 8)
@itest_custom("ldrd r2, [sp]")
def test_ldrd(self):
r2 = 0x41
r3 = 0x42
self.cpu.stack_push(r3)
self.cpu.stack_push(r2)
self.cpu.execute()
self.assertEqual(self.rf.read('R2'), r2)
self.assertEqual(self.rf.read('R3'), r3)
@itest_custom("pop {r1}")
def test_pop_one_reg(self):
self.cpu.stack_push(0x55)
@@ -855,6 +865,27 @@ class Armv7CpuInstructions(unittest.TestCase):
new_r2 = self.rf.read('R2')
self.assertEqual(new_r2, r2 + 3)
@itest_custom("strd R2, [R1]")
@itest_setregs("R1=0xD000", "R2=34", "R3=35")
def test_strd(self):
r1 = self.rf.read('R1')
r2 = self.rf.read('R2')
r3 = self.rf.read('R3')
self.cpu.execute()
dr2 = self.cpu.read_int(r1, self.cpu.address_bit_size)
dr3 = self.cpu.read_int(r1+4, self.cpu.address_bit_size)
self.assertEqual(dr2, r2)
self.assertEqual(dr3, r3)
@itest_custom("str R2, [R1]")
@itest_setregs("R1=0xD000", "R2=34")
def test_str(self):
r1 = self.rf.read('R1')
r2 = self.rf.read('R2')
self.cpu.execute()
dr2 = self.cpu.read_int(r1, self.cpu.address_bit_size)
self.assertEqual(dr2, r2)
# BL
@itest_custom("bl 0x170")