diff --git a/manticore/core/cpu/arm.py b/manticore/core/cpu/arm.py
index d5d6fc1..26e28fa 100644
--- a/manticore/core/cpu/arm.py
+++ b/manticore/core/cpu/arm.py
@@ -548,6 +548,36 @@ class Armv7Cpu(Cpu):
                         return
         raise NotImplementedError("MRC: unimplemented combination of coprocessor, opcode, and coprocessor register")
 
+    @instruction
+    def LDRD(cpu, dest1, dest2, src, offset=None):
+        '''
+        Loads double width data from memory.
+        '''
+        assert dest1.type == 'register'
+        assert dest2.type == 'register'
+        assert src.type == 'memory'
+        mem1 = cpu.read_int(src.address(), 32)
+        mem2 = cpu.read_int(src.address()+4, 32)
+        writeback = cpu._compute_writeback(src, offset)
+        dest1.write(mem1)
+        dest2.write(mem2)
+        cpu._cs_hack_ldr_str_writeback(src, offset, writeback)
+
+    @instruction
+    def STRD(cpu, src1, src2, dest, offset=None):
+        '''
+        Writes the contents of two registers to memory.
+        '''
+        assert src1.type == 'register'
+        assert src2.type == 'register'
+        assert dest.type == 'memory'
+        val1 = src1.read()
+        val2 = src2.read()
+        writeback = cpu._compute_writeback(dest, offset)
+        cpu.write_int(dest.address(), val1, 32)
+        cpu.write_int(dest.address()+4, val2, 32)
+        cpu._cs_hack_ldr_str_writeback(dest, offset, writeback)
+
     @instruction
     def LDREX(cpu, dest, src, offset=None):
         '''
diff --git a/tests/test_armv7cpu.py b/tests/test_armv7cpu.py
index 0bfb9be..e2c66f9 100644
--- a/tests/test_armv7cpu.py
+++ b/tests/test_armv7cpu.py
@@ -764,6 +764,16 @@ class Armv7CpuInstructions(unittest.TestCase):
         self.assertEqual(self.rf.read('R1'), 42)
         self.assertEqual(self.rf.read('SP'), pre_stack - 8)
 
+    @itest_custom("ldrd r2, [sp]")
+    def test_ldrd(self):
+        r2 = 0x41
+        r3 = 0x42
+        self.cpu.stack_push(r3)
+        self.cpu.stack_push(r2)
+        self.cpu.execute()
+        self.assertEqual(self.rf.read('R2'), r2)
+        self.assertEqual(self.rf.read('R3'), r3)
+
     @itest_custom("pop {r1}")
     def test_pop_one_reg(self):
         self.cpu.stack_push(0x55)
@@ -855,6 +865,27 @@ class Armv7CpuInstructions(unittest.TestCase):
         new_r2 = self.rf.read('R2')
         self.assertEqual(new_r2, r2 + 3)
 
+    @itest_custom("strd R2, [R1]")
+    @itest_setregs("R1=0xD000", "R2=34", "R3=35")
+    def test_strd(self):
+        r1 = self.rf.read('R1')
+        r2 = self.rf.read('R2')
+        r3 = self.rf.read('R3')
+        self.cpu.execute()
+        dr2 = self.cpu.read_int(r1, self.cpu.address_bit_size)
+        dr3 = self.cpu.read_int(r1+4, self.cpu.address_bit_size)
+        self.assertEqual(dr2, r2)
+        self.assertEqual(dr3, r3)
+
+    @itest_custom("str R2, [R1]")
+    @itest_setregs("R1=0xD000", "R2=34")
+    def test_str(self):
+        r1 = self.rf.read('R1')
+        r2 = self.rf.read('R2')
+        self.cpu.execute()
+        dr2 = self.cpu.read_int(r1, self.cpu.address_bit_size)
+        self.assertEqual(dr2, r2)
+
     # BL
 
     @itest_custom("bl 0x170")