7dd0879918
* RegisterFile refactor everywhere * Update arm_rf tests * Refactor Operand in both x86 and arm * Add APSR support (#53) * Add APSR support * #issuecomment-284826572 * APSR tests * cspr to aspr * RegisterFile refactor everywhere * Update arm_rf tests * Refactor Operand in both x86 and arm * Rebased and NotImplementedError fix * ARM register initialization compressed * Fix merging bugs * Assimilate PR comments * Assimilate PR comments2 * The new style. future is now * WIP * Improve quick start ,add asciinema (#58) * Towards a helloworld world * Rm requirements.txt (#56) * Print workspace dir by default (#55) * Print workspace dir by default * Change initial cli output * refactor or or or * WIP * Add arm rf testcase * ARM aliases fix * debug print removed * fix tests * Remove unicorn script from travis build (#64) * remove unicorn script from travis build * remove unicorn script entirely * Rename test -> tests (#66) * rename test -> tests * re-add ignored tests * Switch instructions to prefer virtualenv (#65) * switch instructions to prefer virtualenv * document use of virtualenvwrapper * Make cpuid more forgiving (#67) * Make cpuid more forgiving * error() to warning() * Add CPUID EAX=0xd ECX=0,1 * Let logger handle the format string iff needed * to hex * Rm unused files (#76) * Move state into own file (#75) * Move State from executor.py * Fix import * relative import * Rm unnecessary code (#80) * Add example crackme (#77) * add example crackme * make filename and directory structure more accurate * Fix state.branches (#74) * init * rm old code pretty sure it's wrong * Clean * rm * Rename record_fork, move to ConcretizeRegister exception handler It doesn't need to be in fork() because it's only relevant for when we fork due to PC. * Add test for record_branches * Add back record_branches which got removed in rebase Rebase went oddly because State got moved to a new file * unnecesary tuple() * necesary tuple * remove unnecessary keys() * Use OrderedDict (#84) It can be useful to know elements in `branches` towards the end are more recently discovered branches * arm: Fix broken dynamic APSR (#78) * Refactor Register (#82) * Fix register read bug If we store a BitVec, we do NOT want to return bool() of it, which returns True, which is totally incorrect. We do however, want to return a symbolic Bool of it, if it is a 1 bit register (flag). * Improve * Raise error * Fix register tests Changed the interfaces: - removed nbits param (never used) - no longer raise AssertionError when overflowing a flag reg, just truncate - rename test funcs to be more descriptive * rm unused import * Add symbolic tests * Rm no longer applicable test * Add docs (#61) * Add sphinx-quickstart generated docs * Add api.rst * Edit index.rst * Add autodocumenting Manticore class * Update Manticore docstring * Doc verbosity * Doc hook and add_hook * More docs * Add Sphinx dev dep For building docs * RegisterFile refactor everywhere * Update arm_rf tests * Refactor Operand in both x86 and arm * RegisterFile refactor everywhere * Refactor Operand in both x86 and arm * Rebased and NotImplementedError fix * ARM register initialization compressed * Fix merging bugs * Assimilate PR comments * Assimilate PR comments2 * The new style. future is now * WIP * Towards a helloworld world * refactor or or or * WIP * Add arm rf testcase * ARM aliases fix * debug print removed * fix tests * unnecesary tuple() * necesary tuple * remove unnecessary keys() * rebased * Remove test * https://github.com/trailofbits/manticore/pull/57#pullrequestreview-27971778 * https://github.com/trailofbits/manticore/pull/57#discussion_r107820815, https://github.com/trailofbits/manticore/pull/57#discussion_r107820331 * https://github.com/trailofbits/manticore/pull/57#discussion_r107821090 * https://github.com/trailofbits/manticore/pull/57#discussion_r107821066 * https://github.com/trailofbits/manticore/pull/57#discussion_r107821919 * OOps search and replace * (invalid) -> None * The (invalid) -> None * None vs. invalid * In armpy we know that STACK is SP so lets try to eliminate cpu.STACK in favor of x.SP * remove ugly hex * Removed redundant import and comment
76 lines
2.5 KiB
Python
76 lines
2.5 KiB
Python
import unittest
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from manticore.core.cpu.arm import Armv7RegisterFile as RF
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from manticore.core.cpu.arm import *
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from capstone.arm import *
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class Armv7RF(unittest.TestCase):
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def setUp(self):
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self.r = RF()
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def test_init_state(self):
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self.assertEqual(self.r.read('R0'), 0)
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def test_write_read(self):
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self.r.write('R0', 1)
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self.assertEqual(self.r.read('R0'), 1)
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def test_write_read_sp(self):
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self.r.write('SP', 1)
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self.assertEqual(self.r.read('SP'), 1)
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def test_flag_wr(self):
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self.r.write('APSR_Z', True)
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self.assertEqual(self.r.read('APSR_Z'), True)
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def test_flag_wr_f(self):
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self.r.write('APSR_Z', False)
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self.assertEqual(self.r.read('APSR_Z'), False)
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def test_bad_reg_name(self):
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with self.assertRaises(AssertionError):
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nonexistant_reg = "Pc"
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self.r.read(nonexistant_reg)
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def test_flag_wr(self):
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self.r.write('APSR', 0xffffffff)
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self.assertEqual(self.r.read('APSR'), 0xf0000000) #4 more significant bits used
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self.assertEqual(self.r.read('APSR_V'), True)
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self.assertEqual(self.r.read('APSR_C'), True)
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self.assertEqual(self.r.read('APSR_Z'), True)
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self.assertEqual(self.r.read('APSR_N'), True)
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self.r.write('APSR_N', False)
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self.assertEqual(self.r.read('APSR'), 0x70000000)
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self.r.write('APSR_Z', False)
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self.assertEqual(self.r.read('APSR'), 0x30000000)
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self.r.write('APSR_C', False)
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self.assertEqual(self.r.read('APSR'), 0x10000000)
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self.r.write('APSR_V', False)
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self.assertEqual(self.r.read('APSR'), 0x00000000)
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def test_register_independence_wr(self):
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regs = ( 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6', 'R7', 'R8',
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'R9', 'R10', 'R11', 'R12', 'R13', 'R14', 'R15' )
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aliases = {'SB':'R9', 'SL':'R10', 'FP':'R11', 'IP': 'R12', 'STACK': 'R13', 'SP': 'R13', 'LR': 'R14', 'PC': 'R15' }
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for j in xrange(16):
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for i in xrange(16):
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if i == j:
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self.r.write(regs[i], 0x41424344)
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else:
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self.r.write(regs[i], 0)
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for a,b in aliases.items():
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self.assertEqual(self.r.read(a), self.r.read(b))
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for i in xrange(16):
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if i == j:
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self.assertEqual(self.r.read(regs[i]), 0x41424344 )
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else:
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self.assertEqual(self.r.read(regs[i]), 0x00000000 )
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