9c19014e4b
* Fix duplicate armv7rf test name * Small refactor of armv7rf * Proper test classes names
76 lines
2.5 KiB
Python
76 lines
2.5 KiB
Python
import unittest
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from manticore.core.cpu.arm import Armv7RegisterFile as RF
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class Armv7RFTest(unittest.TestCase):
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_multiprocess_can_split_ = True
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def setUp(self):
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self.r = RF()
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def test_init_state(self):
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self.assertEqual(self.r.read('R0'), 0)
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def test_write_read(self):
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self.r.write('R0', 1)
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self.assertEqual(self.r.read('R0'), 1)
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def test_write_read_sp(self):
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self.r.write('SP', 1)
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self.assertEqual(self.r.read('SP'), 1)
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def test_flag_wr(self):
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self.r.write('APSR_Z', True)
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self.assertEqual(self.r.read('APSR_Z'), True)
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def test_flag_wr_f(self):
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self.r.write('APSR_Z', False)
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self.assertEqual(self.r.read('APSR_Z'), False)
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def test_bad_reg_name(self):
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with self.assertRaises(AssertionError):
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nonexistant_reg = "Pc"
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self.r.read(nonexistant_reg)
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def test_flag_wr_aspr(self):
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self.r.write('APSR', 0xffffffff)
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self.assertEqual(self.r.read('APSR'), 0xf0000000) # 4 more significant bits used
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self.assertEqual(self.r.read('APSR_V'), True)
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self.assertEqual(self.r.read('APSR_C'), True)
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self.assertEqual(self.r.read('APSR_Z'), True)
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self.assertEqual(self.r.read('APSR_N'), True)
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self.r.write('APSR_N', False)
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self.assertEqual(self.r.read('APSR'), 0x70000000)
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self.r.write('APSR_Z', False)
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self.assertEqual(self.r.read('APSR'), 0x30000000)
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self.r.write('APSR_C', False)
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self.assertEqual(self.r.read('APSR'), 0x10000000)
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self.r.write('APSR_V', False)
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self.assertEqual(self.r.read('APSR'), 0x00000000)
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def test_register_independence_wr(self):
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regs = ('R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6', 'R7', 'R8',
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'R9', 'R10', 'R11', 'R12', 'R13', 'R14', 'R15')
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aliases = {'SB': 'R9', 'SL': 'R10', 'FP': 'R11', 'IP': 'R12', 'STACK': 'R13', 'SP': 'R13', 'LR': 'R14',
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'PC': 'R15'}
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for j in xrange(16):
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for i in xrange(16):
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if i == j:
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self.r.write(regs[i], 0x41424344)
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else:
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self.r.write(regs[i], 0)
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for a, b in aliases.items():
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self.assertEqual(self.r.read(a), self.r.read(b))
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for i in xrange(16):
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if i == j:
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self.assertEqual(self.r.read(regs[i]), 0x41424344)
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else:
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self.assertEqual(self.r.read(regs[i]), 0x00000000)
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