DeforaNetworks/manticore
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Update MOV implementation (carry) (#105)

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* Update MOV implementation wrt carry
* Remove intermediate flags dict
* Fix register reference
* Document MOV to conform with current standard
This commit is contained in:
Yan 2017-03-24 17:55:24 -04:00 committed by GitHub
parent 7dd0879918
commit f0a6f66d77
2 changed files with 18 additions and 15 deletions
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21
manticore/core/cpu/arm.py
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@ -471,21 +471,18 @@ class Armv7Cpu(Cpu):
@instruction
def MOV(cpu, dest, src):
'''TODO: MOV imm should technically set carry bit.
XXX: We now set carry bit when it's a shift operation
'''
Implement the MOV{S} instruction.
Note: If src operand is PC, temporarily release our logical PC
view and conform to the spec, which dictates PC = curr instr + 8
'''
result, carry = src.read(withCarry=True)
dest.write(result)
# Setting flags in two separate setFlags calls clears earlier flags, set
# it once
flags = {'N' : HighBit(result),
'Z': (result == 0)}
if src.is_shifted():
flags['C'] = carry
cpu.setFlags(**flags)
:param Armv7Operand dest: The destination operand; register.
:param Armv7Operand src: The source operand; register or immediate.
'''
result, carry_out = src.read(withCarry=True)
dest.write(result)
cpu.setFlags(C=carry_out, N=HighBit(result), Z=(result == 0))
def _handleWriteback(cpu, src, dest, offset):
# capstone bug doesn't set writeback correctly for postindex reg

10
tests/test_armv7cpu.py
View File

@ -234,11 +234,17 @@ class Armv7CpuInstructions(unittest.TestCase):
@itest_custom("movs r0, 0xff000000")
def test_movs_imm_modified_imm_max(self):
pre_c = self.rf.read('APSR_C')
pre_v = self.rf.read('APSR_V')
self.cpu.execute()
self.assertEqual(self.rf.read('R0'), 0xff000000)
self._checkFlagsNZCV(1, 0, pre_c, pre_v)
self._checkFlagsNZCV(1, 0, 1, pre_v)
@itest_custom("movs r0, 0x0e000000")
def test_movs_imm_modified_imm_sans_carry(self):
pre_v = self.rf.read('APSR_V')
self.cpu.execute()
self.assertEqual(self.rf.read('R0'), 0x0e000000)
self._checkFlagsNZCV(0, 0, 0, pre_v)
@itest_custom("movs r0, r1")
def test_movs_reg(self):