From a52be7459d8d03dced30a16e91d728e0147bedc3 Mon Sep 17 00:00:00 2001
From: Mark Mossberg <mark.mossberg@gmail.com>
Date: Thu, 20 Apr 2017 15:30:50 -0400
Subject: [PATCH] Arm add vldmia (#154)

* Add VLDMIA

* Add vldmia tests
---
 manticore/core/cpu/arm.py |  4 ++++
 tests/test_armv7cpu.py    | 26 ++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/manticore/core/cpu/arm.py b/manticore/core/cpu/arm.py
index c8ebc40..d1ca606 100644
--- a/manticore/core/cpu/arm.py
+++ b/manticore/core/cpu/arm.py
@@ -840,6 +840,10 @@ class Armv7Cpu(Cpu):
         if cpu.instruction.writeback:
             base.writeback(updated_address)
 
+    @instruction
+    def VLDMIA(cpu, base, *regs):
+        cpu._LDM(ARM_INS_VLDMIA, base, regs)
+
     @instruction
     def STCL(cpu, *operands):
         pass
diff --git a/tests/test_armv7cpu.py b/tests/test_armv7cpu.py
index be60626..9d670f7 100644
--- a/tests/test_armv7cpu.py
+++ b/tests/test_armv7cpu.py
@@ -1352,3 +1352,29 @@ class Armv7CpuInstructions(unittest.TestCase):
     def test_dmb(self):
         # This is a nop, ensure that the instruction exists
         self.assertTrue(True)
+
+    @itest_custom("vldmia  r1, {d8, d9, d10}")
+    def test_vldmia(self):
+        self.cpu.stack_push(20)
+        self.cpu.stack_push(21)
+        self.cpu.stack_push(22)
+        self.cpu.R1 = self.cpu.SP
+        pre = self.cpu.R1
+        self.cpu.execute()
+        self.assertEqual(self.cpu.D8, 22)
+        self.assertEqual(self.cpu.D9, 21)
+        self.assertEqual(self.cpu.D10, 20)
+        self.assertEqual(self.cpu.R1, pre)
+
+    @itest_custom("vldmia  r1!, {d8, d9, d10}")
+    def test_vldmia_wb(self):
+        pre = self.cpu.SP
+        self.cpu.stack_push(20)
+        self.cpu.stack_push(21)
+        self.cpu.stack_push(22)
+        self.cpu.R1 = self.cpu.SP
+        self.cpu.execute()
+        self.assertEqual(self.cpu.D8, 22)
+        self.assertEqual(self.cpu.D9, 21)
+        self.assertEqual(self.cpu.D10, 20)
+        self.assertEqual(self.cpu.R1, pre)