diff --git a/manticore/core/cpu/abstractcpu.py b/manticore/core/cpu/abstractcpu.py
index 6faded3..bca4c9d 100644
--- a/manticore/core/cpu/abstractcpu.py
+++ b/manticore/core/cpu/abstractcpu.py
@@ -31,7 +31,7 @@ class Operand(object):
         scale = property( lambda self: self.parent.op.mem.scale )
         disp = property( lambda self: self.parent.op.mem.disp )
 
-    def __init__(self, cpu, op, **kwargs):
+    def __init__(self, cpu, op):
         '''
         This encapsulates the arch-independent way to access instruction
         operands and immediates based on a capstone operand descriptor. This
@@ -82,8 +82,7 @@ class Operand(object):
         ''' It writes the value of specific type to the registers or memory '''
         raise NotImplementedError
 
-# Basic register file structure not actully need to abstract as it's used only'
-# from the cpu implementation
+# Basic register file structure not actually need to abstract as it's used only from the cpu implementation
 class RegisterFile(object):
 
     def __init__(self, aliases=None):
@@ -360,7 +359,7 @@ class Cpu(object):
                         break
                 assert isinstance(c, str)
                 text += c
-        except MemoryException as e:
+        except MemoryException:
             pass
         
         code = text.ljust(self.max_instr_width, '\x00')
@@ -462,7 +461,6 @@ class Cpu(object):
                 result += "%3s: 0x%016x"%(reg_name, value)
             else:
                 result += "%3s: %r"%(reg_name, value)
-            pos = 0
             result += '\n'
 
         return result
@@ -496,7 +494,7 @@ class DivideError(Exception):
     pass
 
 class CpuInterrupt(Exception):
-    ''' Any interruption triggred by the CPU '''
+    ''' Any interruption triggered by the CPU '''
     pass
 
 class Interruption(CpuInterrupt):
diff --git a/manticore/core/cpu/arm.py b/manticore/core/cpu/arm.py
index 074a55f..92de6a8 100644
--- a/manticore/core/cpu/arm.py
+++ b/manticore/core/cpu/arm.py
@@ -115,7 +115,6 @@ class Armv7Operand(Operand):
 
     def address(self):
         assert self.op.type == ARM_OP_MEM
-        mem = self.op.mem
         addr = self.get_mem_base_addr() + self.get_mem_offset()
         return addr & Mask(self.cpu.address_bit_size)
 
@@ -265,7 +264,7 @@ class Armv7Cpu(Cpu):
     mode = CS_MODE_ARM
 
 
-    def __init__(self, memory, *args, **kwargs):
+    def __init__(self, memory):
         super(Armv7Cpu, self).__init__(Armv7RegisterFile(), memory)
         self._last_flags = {'C': 0, 'V': 0, 'N': 0, 'Z': 0}
         self._force_next = False
@@ -736,7 +735,7 @@ class Armv7Cpu(Cpu):
 
     @instruction
     def SVC(cpu, op):
-        if (op.read() != 0):
+        if op.read() != 0:
             logger.warning("Bad SVC number: {:08}".format(op.read()))
         raise Interruption(0)
 
diff --git a/tests/test_armv7cpu.py b/tests/test_armv7cpu.py
index 233117c..be60626 100644
--- a/tests/test_armv7cpu.py
+++ b/tests/test_armv7cpu.py
@@ -24,7 +24,7 @@ def assemble(asm):
 
 class Armv7CpuTest(unittest.TestCase):
     def setUp(self):
-        self.c = Cpu(Memory32(), 'armv7')
+        self.c = Cpu(Memory32())
         self.rf = self.c.regfile
         self._setupStack()
 
@@ -134,7 +134,7 @@ def itest_custom(asm):
 
 class Armv7CpuInstructions(unittest.TestCase):
     def setUp(self):
-        self.cpu = Cpu(Memory32(), 'armv7')
+        self.cpu = Cpu(Memory32())
         self.mem = self.cpu.memory
         self.rf = self.cpu.regfile
 
diff --git a/tests/test_cpu_manual.py b/tests/test_cpu_manual.py
index b5ea307..d730972 100644
--- a/tests/test_cpu_manual.py
+++ b/tests/test_cpu_manual.py
@@ -1,3 +1,4 @@
+import struct
 import unittest
 from manticore.core.cpu.x86 import *
 from manticore.core.smtlib import Operators
diff --git a/tests/test_unicorn.py b/tests/test_unicorn.py
index 2978f49..2ca5b26 100644
--- a/tests/test_unicorn.py
+++ b/tests/test_unicorn.py
@@ -90,7 +90,7 @@ class Armv7UnicornInstructions(unittest.TestCase):
     all semantics match.
     '''
     def setUp(self):
-        self.cpu = Cpu(Memory32(), 'armv7')
+        self.cpu = Cpu(Memory32())
         self.mem = self.cpu.memory
         self.rf = self.cpu.regfile