diff --git a/manticore/core/cpu/arm.py b/manticore/core/cpu/arm.py
index 078c006..279b91a 100644
--- a/manticore/core/cpu/arm.py
+++ b/manticore/core/cpu/arm.py
@@ -440,6 +440,8 @@ class Armv7Cpu(Cpu):
                 return 'LSR'
             elif instr.mnemonic.startswith('lsl'):
                 return 'LSL'
+            elif instr.mnemonic.startswith('asr'):
+                return 'ASR'
         return OP_NAME_MAP.get(name, name)
 
     def readOperand(self, op):