DeforaNetworks/hashcat
DeforaNetworks/hashcat
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hashcat/OpenCL
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Jens Steube 1f22984313 The hc_bytealign_be_S() was merged too early, but is not yet used anywhere for this platform so we can remove it again.
2021-08-12 15:15:32 +02:00
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amp_a0.cl
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amp_a1.cl
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amp_a3.cl
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inc_cipher_aes-gcm.cl
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inc_cipher_aes-gcm.h
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inc_cipher_aes.cl
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inc_cipher_aes.h
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inc_cipher_camellia.cl
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inc_cipher_camellia.h
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inc_cipher_des.cl
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inc_cipher_des.h
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inc_cipher_kuznyechik.cl
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inc_cipher_kuznyechik.h
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inc_cipher_rc4.cl
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inc_cipher_rc4.h
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inc_cipher_serpent.cl
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inc_cipher_serpent.h
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inc_cipher_twofish.cl
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inc_cipher_twofish.h
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inc_common.cl
The hc_bytealign_be_S() was merged too early, but is not yet used anywhere for this platform so we can remove it again.
2021-08-12 15:15:32 +02:00
inc_common.h
Update module, add a0 and a1 optimized kernels
2021-08-04 01:39:47 -04:00
inc_comp_multi_bs.cl
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inc_comp_multi_bs.h
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inc_comp_multi.cl
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inc_comp_multi.h
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inc_comp_single_bs.cl
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inc_comp_single_bs.h
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inc_comp_single.cl
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inc_comp_single.h
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inc_diskcryptor_xts.cl
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inc_diskcryptor_xts.h
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inc_ecc_secp256k1.cl
AMD GPUs: On Apple OpenCL platform, we ask for the preferred kernel thread size rather than hard-coding 32
2021-07-27 09:37:31 +02:00
inc_ecc_secp256k1.h
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inc_hash_blake2b.cl
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
inc_hash_blake2b.h
Optimize BLAKE2B_ROUND() 64 bit rotates
2021-07-17 18:18:22 +02:00
inc_hash_md4.cl
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inc_hash_md4.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_md5.cl
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inc_hash_md5.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_ripemd160.cl
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inc_hash_ripemd160.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha1.cl
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inc_hash_sha1.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha224.cl
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inc_hash_sha224.h
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inc_hash_sha256.cl
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inc_hash_sha256.h
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inc_hash_sha384.cl
Fixed datatype in function sha384_hmac_init_vector_128() that could come into effect if vector datatype was manually set
2021-07-19 15:58:38 +02:00
inc_hash_sha384.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha512.cl
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inc_hash_sha512.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_streebog256.cl
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inc_hash_streebog256.h
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inc_hash_streebog512.cl
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inc_hash_streebog512.h
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inc_hash_whirlpool.cl
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inc_hash_whirlpool.h
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inc_luks_aes.cl
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inc_luks_aes.h
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inc_luks_af.cl
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inc_luks_af.h
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inc_luks_essiv.cl
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inc_luks_essiv.h
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inc_luks_serpent.cl
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inc_luks_serpent.h
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inc_luks_twofish.cl
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inc_luks_twofish.h
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inc_luks_xts.cl
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inc_luks_xts.h
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inc_platform.cl
Update module_unstable_warning() for -m 172xx on HIP
2021-07-23 21:09:55 +02:00
inc_platform.h
Switch HIP vector datatypes to OpenCL like ext_vector_type()
2021-07-19 20:24:30 +02:00
inc_rp_optimized.cl
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp_optimized.h
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp.cl
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp.h
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_scalar.cl
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inc_scalar.h
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inc_simd.cl
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inc_simd.h
Fixed false negative in all VeraCrypt hash-modes if both conditions are met: 1. use CPU for cracking and 2. PIM range was used
2021-07-20 11:31:31 +02:00
inc_truecrypt_crc32.cl
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inc_truecrypt_crc32.h
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inc_truecrypt_keyfile.cl
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inc_truecrypt_keyfile.h
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inc_truecrypt_xts.cl
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inc_truecrypt_xts.h
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inc_types.h
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
inc_vendor.h
Work around segmentation fault in Intel JiT 2021.12.6.0.19_160000 compiling hc_enc_next()/hc_enc_next_global()
2021-08-03 08:34:37 +02:00
inc_veracrypt_keyfile.cl
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inc_veracrypt_keyfile.h
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inc_veracrypt_xts.cl
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inc_veracrypt_xts.h
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inc_zip_inflate.cl
Add missing u64 vector datatypes mapping for OpenCL
2021-07-27 09:54:15 +02:00
m00000_a0-optimized.cl
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m00000_a0-pure.cl
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m00000_a1-optimized.cl
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m00000_a1-pure.cl
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m00160_a0-pure.cl
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m00160_a1-optimized.cl
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m00160_a1-pure.cl
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m00170_a0-pure.cl
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m00170_a1-optimized.cl
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m00200_a0-optimized.cl
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m00200_a1-optimized.cl
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m00200_a3-optimized.cl
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m00300_a0-pure.cl
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m00300_a1-optimized.cl
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m00300_a1-pure.cl
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m00300_a3-optimized.cl
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m00300_a3-pure.cl
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m00400-optimized.cl
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m00400-pure.cl
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m00500-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m00500-pure.cl
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m00600_a0-optimized.cl
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m00600_a0-pure.cl
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m00600_a1-optimized.cl
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m00600_a3-optimized.cl
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m00900_a0-optimized.cl
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m00900_a1-optimized.cl
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m01500_a3-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m01600-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m01600-pure.cl
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m01700_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a0-pure.cl
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m01700_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a1-pure.cl
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m01700_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a3-pure.cl
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m01710_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a0-pure.cl
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m01710_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a1-pure.cl
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m01710_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a3-pure.cl
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m01720_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a0-pure.cl
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m01720_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a1-pure.cl
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m01720_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a3-pure.cl
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m01730_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a0-pure.cl
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m01730_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a1-pure.cl
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m01730_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a3-pure.cl
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m01740_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a0-pure.cl
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m01740_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a1-pure.cl
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m01740_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a3-pure.cl
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m01750_a0-optimized.cl
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m01750_a0-pure.cl
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m02410_a3-optimized.cl
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m02500-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
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Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
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m04900_a1-pure.cl
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m04900_a3-optimized.cl
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m04900_a3-pure.cl
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m05000_a0-pure.cl
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m05000_a1-pure.cl
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m05000_a3-optimized.cl
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m05000_a3-pure.cl
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m05100_a0-pure.cl
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m05100_a1-pure.cl
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m05100_a3-optimized.cl
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m05200-pure.cl
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m05300_a0-pure.cl
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m05300_a1-optimized.cl
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m05300_a1-pure.cl
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m05300_a3-optimized.cl
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m05300_a3-pure.cl
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m05400_a0-pure.cl
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m05400_a1-optimized.cl
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m05400_a1-pure.cl
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m05400_a3-optimized.cl
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m05400_a3-pure.cl
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m05500_a0-optimized.cl
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m05500_a0-pure.cl
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m05500_a1-optimized.cl
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m05500_a1-pure.cl
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m05500_a3-optimized.cl
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m05600_a0-pure.cl
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m05600_a1-optimized.cl
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m05600_a1-pure.cl
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m05600_a3-optimized.cl
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m05600_a3-pure.cl
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m05800-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m05800-pure.cl
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m06000_a0-optimized.cl
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m06000_a0-pure.cl
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m06000_a1-optimized.cl
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m06000_a3-optimized.cl
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m06100_a0-pure.cl
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m06100_a1-pure.cl
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m06300-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m06300-pure.cl
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m06500-pure.cl
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m06600-pure.cl
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m07000_a0-pure.cl
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m07000_a1-optimized.cl
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m07000_a3-optimized.cl
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m07000_a3-pure.cl
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m07100-pure.cl
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m07300_a0-optimized.cl
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m07300_a0-pure.cl
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m07300_a1-optimized.cl
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m07300_a1-pure.cl
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m07300_a3-optimized.cl
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m07300_a3-pure.cl
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m07400-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m07400-pure.cl
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m07500_a0-optimized.cl
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m07500_a0-pure.cl
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m07500_a1-optimized.cl
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m07500_a1-pure.cl
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m07500_a3-optimized.cl
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m07500_a3-pure.cl
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m07700_a0-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07700_a1-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07700_a3-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a0-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a1-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a3-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07800_a0-optimized.cl
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m07800_a1-optimized.cl
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m07800_a3-optimized.cl
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m07801_a0-optimized.cl
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m07801_a1-optimized.cl
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m07801_a3-optimized.cl
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m07900-pure.cl
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m08000_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08000_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08000_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08100_a0-optimized.cl
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m08100_a0-pure.cl
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m08100_a1-optimized.cl
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m08800-pure.cl
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m08900-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m09000-pure.cl
Password Safe v2: Backport optimizations reducing bank conflicts in bcrypt
2021-07-26 10:17:21 +02:00
m09100-pure.cl
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m09400-pure.cl
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m10300-pure.cl
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m10500-pure.cl
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m10700-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m10700-pure.cl
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m10800_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a0-pure.cl
…
m10800_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a1-pure.cl
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m10800_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a3-pure.cl
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m10810_a0-optimized.cl
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m10810_a0-pure.cl
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m11600-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m11700_a0-optimized.cl
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m12300-pure.cl
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m12500-pure.cl
Fix self-test functionality if FIXED_LOCAL_SIZE_COMP is used
2021-08-02 12:00:17 +02:00
m12600_a0-optimized.cl
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m13600-pure.cl
fix buffer sizes for -m 13600 = WinZip
2021-07-30 15:23:33 +02:00
m13711-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13712-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13713-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13721-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13722-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13723-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13731-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13732-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13733-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13751-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13752-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13753-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13771-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13772-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13773-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13800_a0-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a0-pure.cl
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m13800_a1-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a1-pure.cl
…
m13800_a3-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a3-pure.cl
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m13900_a0-optimized.cl
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m13900_a0-pure.cl
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m13900_a1-optimized.cl
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m13900_a1-pure.cl
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m13900_a3-optimized.cl
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m13900_a3-pure.cl
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m14000_a0-pure.cl
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m14000_a1-pure.cl
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m14000_a3-pure.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m14100_a0-pure.cl
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m15500_a3-optimized.cl
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m15500_a3-pure.cl
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m15600-pure.cl
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m15700-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m15900-pure.cl
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m16000_a0-pure.cl
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m16100_a3-optimized.cl
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m16100_a3-pure.cl
…
m16200-pure.cl
…
m16300-pure.cl
…
m16400_a0-optimized.cl
…
m16400_a0-pure.cl
…
m16400_a1-optimized.cl
…
m16400_a1-pure.cl
…
m16400_a3-optimized.cl
…
m16400_a3-pure.cl
…
m16511_a0-pure.cl
…
m16511_a1-pure.cl
…
m16511_a3-pure.cl
…
m16512_a0-pure.cl
…
m16512_a1-pure.cl
…
m16512_a3-pure.cl
…
m16513_a0-pure.cl
…
m16513_a1-pure.cl
…
m16513_a3-pure.cl
…
m16600_a0-optimized.cl
…
m16600_a0-pure.cl
…
m16600_a1-optimized.cl
…
m16600_a1-pure.cl
…
m16600_a3-optimized.cl
…
m16600_a3-pure.cl
…
m16800-pure.cl
…
m16801-pure.cl
…
m16900-pure.cl
…
m17200_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17200_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17200_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17300_a0-optimized.cl
…
m17300_a1-optimized.cl
…
m17300_a3-optimized.cl
…
m17400_a0-optimized.cl
…
m17400_a1-optimized.cl
…
m17400_a3-optimized.cl
…
m17500_a0-optimized.cl
…
m17500_a1-optimized.cl
…
m17500_a3-optimized.cl
…
m17600_a0-optimized.cl
…
m17600_a1-optimized.cl
…
m17600_a3-optimized.cl
…
m17700_a0-optimized.cl
…
m17700_a1-optimized.cl
…
m17700_a3-optimized.cl
…
m17800_a0-optimized.cl
…
m17800_a1-optimized.cl
…
m17800_a3-optimized.cl
…
m17900_a0-optimized.cl
…
m17900_a1-optimized.cl
…
m17900_a3-optimized.cl
…
m18000_a0-optimized.cl
…
m18000_a1-optimized.cl
…
m18000_a3-optimized.cl
…
m18100_a0-pure.cl
…
m18100_a1-pure.cl
…
m18100_a3-pure.cl
…
m18200_a0-optimized.cl
…
m18200_a0-pure.cl
…
m18200_a1-optimized.cl
…
m18200_a1-pure.cl
…
m18200_a3-optimized.cl
…
m18200_a3-pure.cl
…
m18300-pure.cl
…
m18400-pure.cl
…
m18500_a0-pure.cl
…
m18500_a1-pure.cl
…
m18500_a3-pure.cl
…
m18600-pure.cl
Blowfish Kernels: Backport optimizations reducing bank conflicts from bcrypt to Password Safe v2 and Open Document Format (ODF) 1.1
2021-07-26 13:38:39 +02:00
m18700_a0-optimized.cl
…
m18700_a0-pure.cl
…
m18700_a1-optimized.cl
…
m18700_a1-pure.cl
…
m18700_a3-optimized.cl
…
m18700_a3-pure.cl
…
m18800-pure.cl
…
m18900-pure.cl
…
m19000-pure.cl
…
m19100-pure.cl
…
m19200-pure.cl
…
m19300_a0-pure.cl
…
m19300_a1-pure.cl
…
m19300_a3-pure.cl
…
m19500_a0-pure.cl
…
m19500_a1-pure.cl
…
m19500_a3-pure.cl
…
m19600-pure.cl
Fix variable declaration block level in -m 19600 and -m 19700
2021-07-13 22:22:53 +02:00
m19700-pure.cl
Fix variable declaration block level in -m 19600 and -m 19700
2021-07-13 22:22:53 +02:00
m19800-pure.cl
…
m19900-pure.cl
…
m20011-pure.cl
…
m20012-pure.cl
…
m20013-pure.cl
…
m20500_a0-pure.cl
…
m20500_a1-pure.cl
…
m20500_a3-pure.cl
…
m20510_a0-pure.cl
…
m20510_a1-pure.cl
…
m20510_a3-pure.cl
…
m20600-pure.cl
…
m20710_a0-optimized.cl
…
m20710_a0-pure.cl
…
m20710_a1-optimized.cl
…
m20710_a1-pure.cl
…
m20710_a3-optimized.cl
…
m20710_a3-pure.cl
…
m20720_a0-pure.cl
…
m20720_a1-pure.cl
…
m20720_a3-pure.cl
…
m20800_a0-optimized.cl
…
m20800_a0-pure.cl
…
m20800_a1-optimized.cl
…
m20800_a1-pure.cl
…
m20800_a3-optimized.cl
…
m20800_a3-pure.cl
…
m20900_a0-optimized.cl
…
m20900_a0-pure.cl
…
m20900_a1-optimized.cl
…
m20900_a1-pure.cl
…
m20900_a3-optimized.cl
…
m20900_a3-pure.cl
…
m21000_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a0-pure.cl
…
m21000_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a1-pure.cl
…
m21000_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a3-pure.cl
…
m21100_a0-optimized.cl
…
m21100_a0-pure.cl
…
m21100_a1-optimized.cl
…
m21100_a1-pure.cl
…
m21100_a3-optimized.cl
…
m21100_a3-pure.cl
…
m21200_a0-optimized.cl
…
m21200_a0-pure.cl
…
m21200_a1-optimized.cl
…
m21200_a1-pure.cl
…
m21200_a3-optimized.cl
…
m21200_a3-pure.cl
…
m21300_a0-pure.cl
…
m21300_a1-pure.cl
…
m21300_a3-pure.cl
…
m21400_a0-optimized.cl
…
m21400_a0-pure.cl
…
m21400_a1-optimized.cl
…
m21400_a1-pure.cl
…
m21400_a3-optimized.cl
…
m21400_a3-pure.cl
…
m21500-pure.cl
…
m21600-pure.cl
…
m21700-pure.cl
…
m21800-pure.cl
…
m22000-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m22001-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m22100-pure.cl
…
m22200_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a0-pure.cl
…
m22200_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a1-pure.cl
…
m22200_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a3-pure.cl
…
m22300_a0-optimized.cl
…
m22300_a0-pure.cl
…
m22300_a1-optimized.cl
…
m22300_a1-pure.cl
…
m22300_a3-optimized.cl
…
m22300_a3-pure.cl
…
m22400-pure.cl
…
m22500_a0-optimized.cl
…
m22500_a0-pure.cl
…
m22500_a1-optimized.cl
…
m22500_a1-pure.cl
…
m22500_a3-optimized.cl
…
m22500_a3-pure.cl
…
m22600-pure.cl
…
m22700-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m22911_a0-pure.cl
…
m22911_a1-pure.cl
…
m22911_a3-pure.cl
…
m22921_a0-pure.cl
…
m22921_a1-pure.cl
…
m22921_a3-pure.cl
…
m22931_a0-pure.cl
…
m22931_a1-pure.cl
…
m22931_a3-pure.cl
…
m22941_a0-pure.cl
…
m22941_a1-pure.cl
…
m22941_a3-pure.cl
…
m22951_a0-pure.cl
…
m22951_a1-pure.cl
…
m22951_a3-pure.cl
…
m23001_a0-optimized.cl
…
m23001_a0-pure.cl
…
m23001_a1-optimized.cl
…
m23001_a1-pure.cl
…
m23001_a3-optimized.cl
…
m23001_a3-pure.cl
…
m23002_a0-optimized.cl
…
m23002_a0-pure.cl
…
m23002_a1-optimized.cl
…
m23002_a1-pure.cl
…
m23002_a3-optimized.cl
…
m23002_a3-pure.cl
…
m23003_a0-optimized.cl
…
m23003_a0-pure.cl
…
m23003_a1-optimized.cl
…
m23003_a1-pure.cl
…
m23003_a3-optimized.cl
…
m23003_a3-pure.cl
…
m23100-pure.cl
…
m23200-pure.cl
…
m23300-pure.cl
…
m23400-pure.cl
…
m23500-pure.cl
…
m23600-pure.cl
…
m23700-optimized.cl
…
m23700-pure.cl
Fix self-test functionality if FIXED_LOCAL_SIZE_COMP is used
2021-08-02 12:00:17 +02:00
m23800-optimized.cl
…
m23800-pure.cl
Fix self-test functionality if FIXED_LOCAL_SIZE_COMP is used
2021-08-02 12:00:17 +02:00
m23900-pure.cl
…
m24100-pure.cl
…
m24200-pure.cl
…
m24300_a0-optimized.cl
…
m24300_a0-pure.cl
…
m24300_a1-optimized.cl
…
m24300_a1-pure.cl
…
m24300_a3-optimized.cl
…
m24300_a3-pure.cl
…
m24410-pure.cl
…
m24420-pure.cl
…
m24500-pure.cl
…
m24610-pure.cl
…
m24620-pure.cl
…
m24630-pure.cl
…
m24700_a0-optimized.cl
…
m24700_a0-pure.cl
…
m24700_a1-optimized.cl
…
m24700_a1-pure.cl
…
m24700_a3-optimized.cl
…
m24700_a3-pure.cl
…
m24800_a0-optimized.cl
…
m24800_a0-pure.cl
…
m24800_a1-optimized.cl
…
m24800_a1-pure.cl
…
m24800_a3-optimized.cl
…
m24800_a3-pure.cl
…
m24900_a0-optimized.cl
…
m24900_a1-optimized.cl
…
m24900_a3-optimized.cl
…
m25000-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m25100-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m25200-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m25300-pure.cl
…
m25400-pure.cl
…
m25500-pure.cl
…
m25600-pure.cl
…
m25700_a0-optimized.cl
…
m25700_a1-optimized.cl
…
m25700_a3-optimized.cl
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
m25800-pure.cl
…
m25900-pure.cl
…
m26000_a0-pure.cl
…
m26000_a1-pure.cl
…
m26000_a3-pure.cl
…
m26100-pure.cl
…
m26200_a0-pure.cl
…
m26200_a1-pure.cl
…
m26200_a3-pure.cl
…
m26300_a0-pure.cl
…
m26300_a1-pure.cl
…
m26300_a3-pure.cl
…
m26401_a0-optimized.cl
…
m26401_a1-optimized.cl
…
m26401_a3-optimized.cl
…
m26402_a0-optimized.cl
…
m26402_a1-optimized.cl
…
m26402_a3-optimized.cl
…
m26403_a0-optimized.cl
…
m26403_a1-optimized.cl
…
m26403_a3-optimized.cl
…
m26500-pure.cl
…
m26600-pure.cl
…
m26700-pure.cl
move to 27400, fix unit test
2021-08-10 16:35:15 +02:00
m26800-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m26900-pure.cl
reduced the amount of memory allocated in gpu for SNMPv3 HMAC-SHA384-256
2021-08-03 21:29:07 +02:00
m27000-pure.cl
rename to 27300, reduced the amount of memory allocated in gpu for SNMPv3 HMAC-SHA512-384
2021-08-03 21:42:42 +02:00
m27100-pure.cl
Expect Hex input, removed OPTS_TYPE_PT_ALWAYS_HEXIFY, added benchmark mask.
2021-08-02 11:40:14 +02:00
m27200_a0-optimized.cl
Update m27200_a0-optimized.cl
2021-08-09 18:08:33 +02:00
m27200_a0-pure.cl
Fix errors and make recommended changes, set pw_max to 9 for opti kernel
2021-08-06 09:58:19 -04:00
m27200_a1-optimized.cl
Update m27200_a1-optimized.cl
2021-08-09 18:07:55 +02:00
m27200_a1-pure.cl
Fix errors and make recommended changes, set pw_max to 9 for opti kernel
2021-08-06 09:58:19 -04:00
m27200_a3-optimized.cl
Fix errors and make recommended changes, set pw_max to 9 for opti kernel
2021-08-06 09:58:19 -04:00
m27200_a3-pure.cl
Fix errors and make recommended changes, set pw_max to 9 for opti kernel
2021-08-06 09:58:19 -04:00
m27300-pure.cl
rename to 27300, reduced the amount of memory allocated in gpu for SNMPv3 HMAC-SHA512-384
2021-08-03 21:42:42 +02:00
m27400-pure.cl
move to 27400, fix unit test
2021-08-10 16:35:15 +02:00
markov_be.cl
…
markov_le.cl
…
shared.cl
Implement gpu_bzero
2021-07-17 19:00:10 +03:00