DeforaNetworks/hashcat
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hashcat/OpenCL
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Jens Steube f4e52ca533 Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
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amp_a0.cl
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amp_a1.cl
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amp_a3.cl
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inc_cipher_aes-gcm.cl
add min/max data length limits to MetaMask Wallet
2021-07-04 20:14:25 +02:00
inc_cipher_aes-gcm.h
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inc_cipher_aes.cl
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inc_cipher_aes.h
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inc_cipher_camellia.cl
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inc_cipher_camellia.h
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inc_cipher_des.cl
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inc_cipher_des.h
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inc_cipher_kuznyechik.cl
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inc_cipher_kuznyechik.h
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inc_cipher_rc4.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
inc_cipher_rc4.h
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
inc_cipher_serpent.cl
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inc_cipher_serpent.h
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inc_cipher_twofish.cl
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inc_cipher_twofish.h
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inc_common.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
inc_common.h
Add missing backports from code base v6.2.2
2021-07-11 12:38:59 +02:00
inc_comp_multi_bs.cl
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inc_comp_multi_bs.h
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inc_comp_multi.cl
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inc_comp_multi.h
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inc_comp_single_bs.cl
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inc_comp_single_bs.h
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inc_comp_single.cl
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inc_comp_single.h
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inc_diskcryptor_xts.cl
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inc_diskcryptor_xts.h
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inc_ecc_secp256k1.cl
AMD GPUs: On Apple OpenCL platform, we ask for the preferred kernel thread size rather than hard-coding 32
2021-07-27 09:37:31 +02:00
inc_ecc_secp256k1.h
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inc_hash_blake2b.cl
Optimize BLAKE2B_ROUND() 64 bit rotates
2021-07-17 18:18:22 +02:00
inc_hash_blake2b.h
Optimize BLAKE2B_ROUND() 64 bit rotates
2021-07-17 18:18:22 +02:00
inc_hash_md4.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_md4.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_md5.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_md5.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_ripemd160.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_ripemd160.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha1.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha1.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha224.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha224.h
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inc_hash_sha256.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha256.h
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inc_hash_sha384.cl
Fixed datatype in function sha384_hmac_init_vector_128() that could come into effect if vector datatype was manually set
2021-07-19 15:58:38 +02:00
inc_hash_sha384.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha512.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha512.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_streebog256.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_streebog256.h
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inc_hash_streebog512.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_streebog512.h
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inc_hash_whirlpool.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_whirlpool.h
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inc_luks_aes.cl
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inc_luks_aes.h
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inc_luks_af.cl
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inc_luks_af.h
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inc_luks_essiv.cl
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inc_luks_essiv.h
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inc_luks_serpent.cl
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inc_luks_serpent.h
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inc_luks_twofish.cl
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inc_luks_twofish.h
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inc_luks_xts.cl
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inc_luks_xts.h
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inc_platform.cl
Update module_unstable_warning() for -m 172xx on HIP
2021-07-23 21:09:55 +02:00
inc_platform.h
Switch HIP vector datatypes to OpenCL like ext_vector_type()
2021-07-19 20:24:30 +02:00
inc_rp_optimized.cl
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp_optimized.h
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp.cl
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp.h
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_scalar.cl
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inc_scalar.h
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inc_simd.cl
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inc_simd.h
Fixed false negative in all VeraCrypt hash-modes if both conditions are met: 1. use CPU for cracking and 2. PIM range was used
2021-07-20 11:31:31 +02:00
inc_truecrypt_crc32.cl
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inc_truecrypt_crc32.h
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inc_truecrypt_keyfile.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
inc_truecrypt_keyfile.h
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
inc_truecrypt_xts.cl
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inc_truecrypt_xts.h
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inc_types.h
Add missing u64 vector datatypes mapping for OpenCL
2021-07-27 09:54:15 +02:00
inc_vendor.h
Update module_unstable_warning() for -m 172xx on HIP
2021-07-23 21:09:55 +02:00
inc_veracrypt_keyfile.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
inc_veracrypt_keyfile.h
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
inc_veracrypt_xts.cl
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inc_veracrypt_xts.h
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inc_zip_inflate.cl
Add missing u64 vector datatypes mapping for OpenCL
2021-07-27 09:54:15 +02:00
m00000_a0-optimized.cl
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m00000_a0-pure.cl
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m00000_a1-optimized.cl
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m00000_a1-pure.cl
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m00000_a3-optimized.cl
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m00000_a3-pure.cl
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m00010_a0-optimized.cl
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m00010_a0-pure.cl
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m00010_a1-optimized.cl
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m00010_a1-pure.cl
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m00010_a3-optimized.cl
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m00010_a3-pure.cl
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m00020_a0-optimized.cl
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m00020_a0-pure.cl
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m00020_a1-optimized.cl
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m00020_a1-pure.cl
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m00020_a3-optimized.cl
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m00020_a3-pure.cl
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m00030_a0-optimized.cl
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m00030_a0-pure.cl
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m00030_a1-optimized.cl
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m00030_a1-pure.cl
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m00030_a3-optimized.cl
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m00030_a3-pure.cl
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m00040_a0-optimized.cl
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m00040_a0-pure.cl
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m00040_a1-optimized.cl
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m00040_a1-pure.cl
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m00040_a3-optimized.cl
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m00040_a3-pure.cl
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m00050_a0-optimized.cl
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m00050_a0-pure.cl
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m00050_a1-optimized.cl
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m00050_a1-pure.cl
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m00050_a3-optimized.cl
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m00050_a3-pure.cl
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m00060_a0-optimized.cl
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m00060_a0-pure.cl
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m00060_a1-optimized.cl
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m00060_a1-pure.cl
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m00060_a3-optimized.cl
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m00060_a3-pure.cl
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m00070_a0-optimized.cl
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m00070_a0-pure.cl
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m00070_a1-optimized.cl
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m00070_a1-pure.cl
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m00070_a3-optimized.cl
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m00070_a3-pure.cl
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m00100_a0-optimized.cl
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m00100_a0-pure.cl
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m00100_a1-optimized.cl
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m00100_a1-pure.cl
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m00100_a3-optimized.cl
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m00100_a3-pure.cl
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m00110_a0-optimized.cl
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m00110_a0-pure.cl
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m00110_a1-optimized.cl
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m00110_a1-pure.cl
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m00110_a3-optimized.cl
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m00110_a3-pure.cl
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m00120_a0-optimized.cl
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m00120_a0-pure.cl
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m00120_a1-optimized.cl
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m00120_a1-pure.cl
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m00120_a3-optimized.cl
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m00120_a3-pure.cl
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m00130_a0-optimized.cl
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m00130_a0-pure.cl
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m00130_a1-optimized.cl
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m00130_a1-pure.cl
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m00130_a3-optimized.cl
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m00130_a3-pure.cl
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m00140_a0-optimized.cl
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m00140_a0-pure.cl
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m00140_a1-optimized.cl
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m00140_a1-pure.cl
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m00140_a3-optimized.cl
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m00140_a3-pure.cl
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m00150_a0-optimized.cl
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m00150_a0-pure.cl
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m00150_a1-optimized.cl
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m00150_a1-pure.cl
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m00150_a3-optimized.cl
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m00150_a3-pure.cl
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m00160_a0-optimized.cl
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m00160_a0-pure.cl
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m00160_a1-optimized.cl
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m00160_a1-pure.cl
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m00160_a3-optimized.cl
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m00160_a3-pure.cl
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m00170_a0-optimized.cl
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m00170_a0-pure.cl
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m00170_a1-optimized.cl
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m00170_a1-pure.cl
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m00170_a3-optimized.cl
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m00170_a3-pure.cl
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m00200_a0-optimized.cl
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m00200_a1-optimized.cl
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m00200_a3-optimized.cl
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m00300_a0-optimized.cl
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m00300_a0-pure.cl
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m00300_a1-optimized.cl
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m00300_a1-pure.cl
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m00300_a3-optimized.cl
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m00300_a3-pure.cl
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m00400-optimized.cl
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m00400-pure.cl
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m00500-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m00500-pure.cl
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m00600_a0-optimized.cl
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m00600_a0-pure.cl
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m00600_a1-optimized.cl
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m00600_a1-pure.cl
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m00600_a3-optimized.cl
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m00600_a3-pure.cl
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m00900_a0-optimized.cl
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m00900_a0-pure.cl
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m00900_a1-optimized.cl
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m00900_a1-pure.cl
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m00900_a3-optimized.cl
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m00900_a3-pure.cl
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m01000_a0-optimized.cl
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m01000_a0-pure.cl
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m01000_a1-optimized.cl
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m01000_a1-pure.cl
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m01000_a3-optimized.cl
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m01000_a3-pure.cl
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m01100_a0-optimized.cl
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m01100_a0-pure.cl
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m01100_a1-optimized.cl
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m01100_a1-pure.cl
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m01100_a3-optimized.cl
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m01100_a3-pure.cl
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m01300_a0-optimized.cl
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m01300_a0-pure.cl
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m01300_a1-optimized.cl
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m01300_a1-pure.cl
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m01300_a3-optimized.cl
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m01300_a3-pure.cl
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m01400_a0-optimized.cl
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m01400_a0-pure.cl
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m01400_a1-optimized.cl
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m01400_a1-pure.cl
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m01400_a3-optimized.cl
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m01400_a3-pure.cl
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m01410_a0-optimized.cl
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m01410_a0-pure.cl
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m01410_a1-optimized.cl
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m01410_a1-pure.cl
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m01410_a3-optimized.cl
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m01410_a3-pure.cl
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m01420_a0-optimized.cl
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m01420_a0-pure.cl
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m01420_a1-optimized.cl
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m01420_a1-pure.cl
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m01420_a3-optimized.cl
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m01420_a3-pure.cl
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m01430_a0-optimized.cl
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m01430_a0-pure.cl
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m01430_a1-optimized.cl
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m01430_a1-pure.cl
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m01430_a3-optimized.cl
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m01430_a3-pure.cl
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m01440_a0-optimized.cl
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m01440_a0-pure.cl
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m01440_a1-optimized.cl
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m01440_a1-pure.cl
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m01440_a3-optimized.cl
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m01440_a3-pure.cl
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m01450_a0-optimized.cl
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m01450_a0-pure.cl
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m01450_a1-optimized.cl
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m01450_a1-pure.cl
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m01450_a3-optimized.cl
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m01450_a3-pure.cl
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m01460_a0-optimized.cl
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m01460_a0-pure.cl
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m01460_a1-optimized.cl
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m01460_a1-pure.cl
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m01460_a3-optimized.cl
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m01460_a3-pure.cl
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m01470_a0-optimized.cl
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m01470_a0-pure.cl
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m01470_a1-optimized.cl
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m01470_a1-pure.cl
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m01470_a3-optimized.cl
Modules: Recategorized HASH_CATEGORY option in various modules
2021-05-28 20:06:01 +02:00
m01470_a3-pure.cl
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m01500_a0-pure.cl
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m01500_a1-pure.cl
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m01500_a3-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m01600-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m01600-pure.cl
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m01700_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a0-pure.cl
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m01700_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a1-pure.cl
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m01700_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a3-pure.cl
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m01710_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a0-pure.cl
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m01710_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a1-pure.cl
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m01710_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a3-pure.cl
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m01720_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a0-pure.cl
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m01720_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a1-pure.cl
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m01720_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a3-pure.cl
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m01730_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a0-pure.cl
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m01730_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a1-pure.cl
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m01730_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a3-pure.cl
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m01740_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a0-pure.cl
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m01740_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a1-pure.cl
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m01740_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a3-pure.cl
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m01750_a0-optimized.cl
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m01750_a0-pure.cl
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m01750_a1-optimized.cl
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m01750_a1-pure.cl
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m01750_a3-optimized.cl
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m01750_a3-pure.cl
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m01760_a0-optimized.cl
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m01760_a0-pure.cl
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m01760_a3-optimized.cl
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m01770_a0-optimized.cl
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m01770_a0-pure.cl
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m01770_a1-optimized.cl
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m01770_a1-pure.cl
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m01770_a3-optimized.cl
Modules: Recategorized HASH_CATEGORY option in various modules
2021-05-28 20:06:01 +02:00
m01770_a3-pure.cl
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m01800-optimized.cl
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m01800-pure.cl
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m02000_a0-optimized.cl
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m02100-pure.cl
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m02410_a0-optimized.cl
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m02410_a1-optimized.cl
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m02410_a3-optimized.cl
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m02500-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m02501-pure.cl
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m02610_a0-optimized.cl
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m02610_a0-pure.cl
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m02810_a3-optimized.cl
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m02810_a3-pure.cl
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m03000_a0-pure.cl
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m03000_a1-pure.cl
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m03000_a3-pure.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m03100_a0-optimized.cl
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m03100_a1-optimized.cl
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m03100_a3-optimized.cl
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m03200-pure.cl
BCRYPT Kernels: Improved bcrypt performance by 6.5% for high-end NVIDIA GPU devices using CUDA backend
2021-06-01 22:52:07 +02:00
m03500_a0-optimized.cl
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m03500_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m03500_a1-optimized.cl
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m03500_a1-pure.cl
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m03500_a3-optimized.cl
Update -m 3500 and -m 5000 -a 3 function calls in optimized mode
2021-06-03 07:57:59 +02:00
m03500_a3-pure.cl
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m03710_a0-optimized.cl
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m03800_a3-optimized.cl
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m03800_a3-pure.cl
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m03910_a0-optimized.cl
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m03910_a0-pure.cl
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m03910_a1-optimized.cl
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m03910_a1-pure.cl
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m03910_a3-optimized.cl
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m03910_a3-pure.cl
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m04010_a0-optimized.cl
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m04010_a0-pure.cl
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m04010_a1-optimized.cl
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m04010_a1-pure.cl
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m04010_a3-optimized.cl
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m04010_a3-pure.cl
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m04110_a0-optimized.cl
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m04110_a0-pure.cl
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m04110_a1-optimized.cl
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m04110_a1-pure.cl
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m04110_a3-optimized.cl
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m04110_a3-pure.cl
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m04310_a0-optimized.cl
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m04310_a0-pure.cl
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m04310_a1-optimized.cl
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m04310_a1-pure.cl
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m04310_a3-optimized.cl
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m04310_a3-pure.cl
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m04400_a0-optimized.cl
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m04400_a0-pure.cl
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m04400_a1-optimized.cl
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m04400_a1-pure.cl
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m04400_a3-optimized.cl
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m04400_a3-pure.cl
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m04500_a0-optimized.cl
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m04500_a0-pure.cl
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m04500_a1-optimized.cl
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m04500_a1-pure.cl
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m04500_a3-optimized.cl
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m04500_a3-pure.cl
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m04510_a0-optimized.cl
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m04510_a0-pure.cl
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m04510_a1-optimized.cl
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m04510_a1-pure.cl
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m04510_a3-optimized.cl
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m04510_a3-pure.cl
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m04520_a0-optimized.cl
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m04520_a0-pure.cl
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m04520_a1-optimized.cl
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m04520_a1-pure.cl
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m04520_a3-optimized.cl
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m04520_a3-pure.cl
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m04700_a0-optimized.cl
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m04700_a0-pure.cl
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m04700_a1-optimized.cl
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m04700_a1-pure.cl
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m04700_a3-optimized.cl
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m04700_a3-pure.cl
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m04710_a0-optimized.cl
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m04710_a0-pure.cl
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m04710_a1-optimized.cl
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m04710_a1-pure.cl
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m04710_a3-optimized.cl
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m04710_a3-pure.cl
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m04800_a0-optimized.cl
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m04800_a0-pure.cl
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m04800_a1-optimized.cl
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m04800_a1-pure.cl
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m04800_a3-optimized.cl
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m04800_a3-pure.cl
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m04900_a0-optimized.cl
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m04900_a0-pure.cl
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m04900_a1-optimized.cl
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m04900_a1-pure.cl
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m04900_a3-optimized.cl
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m04900_a3-pure.cl
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m05000_a0-optimized.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m05000_a0-pure.cl
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m05000_a1-optimized.cl
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m05000_a1-pure.cl
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m05000_a3-optimized.cl
Update -m 3500 and -m 5000 -a 3 function calls in optimized mode
2021-06-03 07:57:59 +02:00
m05000_a3-pure.cl
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m05100_a0-optimized.cl
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m05100_a0-pure.cl
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m05100_a1-optimized.cl
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m05100_a1-pure.cl
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m05100_a3-optimized.cl
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m05100_a3-pure.cl
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m05200-pure.cl
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m05300_a0-optimized.cl
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m05300_a0-pure.cl
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m05300_a1-optimized.cl
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m05300_a1-pure.cl
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m05300_a3-optimized.cl
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m05300_a3-pure.cl
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m05400_a0-optimized.cl
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m05400_a0-pure.cl
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m05400_a1-optimized.cl
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m05400_a1-pure.cl
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m05400_a3-optimized.cl
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m05400_a3-pure.cl
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m05500_a0-optimized.cl
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m05500_a0-pure.cl
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m05500_a1-optimized.cl
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m05500_a1-pure.cl
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m05500_a3-optimized.cl
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m05500_a3-pure.cl
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m05600_a0-optimized.cl
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m05600_a0-pure.cl
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m05600_a1-optimized.cl
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m05600_a1-pure.cl
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m05600_a3-optimized.cl
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m05600_a3-pure.cl
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m05800-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m05800-pure.cl
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m06000_a0-optimized.cl
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m06000_a0-pure.cl
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m06000_a1-optimized.cl
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m06000_a1-pure.cl
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m06000_a3-optimized.cl
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m06000_a3-pure.cl
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m06100_a0-optimized.cl
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m06100_a0-pure.cl
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m06100_a1-optimized.cl
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m06100_a1-pure.cl
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m06100_a3-optimized.cl
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m06100_a3-pure.cl
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m06211-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06212-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06213-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06221-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06222-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06223-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06231-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06232-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06233-pure.cl
VeraCrypt: Increase password length support for non-boot volumes from 64 to 128.
2021-06-17 09:45:30 +02:00
m06300-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m06300-pure.cl
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m06400-pure.cl
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m06500-pure.cl
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m06600-pure.cl
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m06700-pure.cl
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m06800-pure.cl
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m06900_a0-optimized.cl
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m06900_a1-optimized.cl
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m06900_a3-optimized.cl
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m07000_a0-optimized.cl
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m07000_a0-pure.cl
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m07000_a1-optimized.cl
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m07000_a1-pure.cl
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m07000_a3-optimized.cl
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m07000_a3-pure.cl
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m07100-pure.cl
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m07300_a0-optimized.cl
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m07300_a0-pure.cl
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m07300_a1-optimized.cl
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m07300_a1-pure.cl
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m07300_a3-optimized.cl
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m07300_a3-pure.cl
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m07400-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m07400-pure.cl
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m07500_a0-optimized.cl
RC4: Updated hash-mode 7500, 9710, 9720, 10400 and 10410 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 19:53:28 +02:00
m07500_a0-pure.cl
RC4: Updated hash-mode 7500, 9710, 9720, 10400 and 10410 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 19:53:28 +02:00
m07500_a1-optimized.cl
RC4: Updated hash-mode 7500, 9710, 9720, 10400 and 10410 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 19:53:28 +02:00
m07500_a1-pure.cl
RC4: Updated hash-mode 7500, 9710, 9720, 10400 and 10410 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 19:53:28 +02:00
m07500_a3-optimized.cl
RC4: Updated hash-mode 7500, 9710, 9720, 10400 and 10410 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 19:53:28 +02:00
m07500_a3-pure.cl
RC4: Updated hash-mode 7500, 9710, 9720, 10400 and 10410 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 19:53:28 +02:00
m07700_a0-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07700_a1-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07700_a3-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a0-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a1-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a3-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07800_a0-optimized.cl
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m07800_a1-optimized.cl
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m07800_a3-optimized.cl
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m07801_a0-optimized.cl
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m07801_a1-optimized.cl
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m07801_a3-optimized.cl
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m07900-pure.cl
…
m08000_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08000_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08000_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08100_a0-optimized.cl
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m08100_a0-pure.cl
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m08100_a1-optimized.cl
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m08100_a1-pure.cl
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m08100_a3-optimized.cl
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m08100_a3-pure.cl
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m08200-pure.cl
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m08300_a0-optimized.cl
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m08300_a0-pure.cl
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m08300_a1-optimized.cl
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m08300_a1-pure.cl
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m08300_a3-optimized.cl
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m08300_a3-pure.cl
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m08400_a0-optimized.cl
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m08400_a0-pure.cl
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m08400_a1-optimized.cl
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m08400_a1-pure.cl
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m08400_a3-optimized.cl
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m08400_a3-pure.cl
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m08500_a0-pure.cl
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m08500_a1-pure.cl
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m08500_a3-pure.cl
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m08600_a0-pure.cl
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m08600_a3-pure.cl
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m08700_a0-optimized.cl
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m08700_a1-optimized.cl
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m08700_a3-optimized.cl
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m08800-pure.cl
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m08900-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m09000-pure.cl
Password Safe v2: Backport optimizations reducing bank conflicts in bcrypt
2021-07-26 10:17:21 +02:00
m09100-pure.cl
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m09400-pure.cl
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m09500-pure.cl
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m09600-pure.cl
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m09700_a0-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m09700_a1-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m09700_a3-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m09710_a0-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m09710_a1-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m09710_a3-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m09720_a0-optimized.cl
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m09720_a1-optimized.cl
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m09720_a3-optimized.cl
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m09800_a0-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09800_a1-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09800_a3-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09810_a0-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09810_a1-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09810_a3-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09820_a0-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09820_a1-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09820_a3-optimized.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m09900_a0-optimized.cl
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m09900_a0-pure.cl
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m09900_a1-optimized.cl
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m09900_a1-pure.cl
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m09900_a3-optimized.cl
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m09900_a3-pure.cl
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m10100_a0-optimized.cl
…
m10100_a1-optimized.cl
…
m10100_a3-optimized.cl
…
m10300-pure.cl
…
m10400_a0-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m10400_a1-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m10400_a3-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m10410_a0-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m10410_a1-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m10410_a3-optimized.cl
RC4: Update -m 97x0 and -m 104x0 to new RC4 crypto library code, improving performance by 20% or more
2021-05-30 15:40:33 +02:00
m10420_a0-optimized.cl
…
m10420_a1-optimized.cl
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m10420_a3-optimized.cl
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m10500-pure.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m10700-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m10700-pure.cl
…
m10800_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a0-pure.cl
…
m10800_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a1-pure.cl
…
m10800_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a3-pure.cl
…
m10810_a0-optimized.cl
…
m10810_a0-pure.cl
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m10810_a1-optimized.cl
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m10810_a1-pure.cl
…
m10810_a3-optimized.cl
…
m10810_a3-pure.cl
…
m10820_a0-optimized.cl
…
m10820_a0-pure.cl
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m10820_a1-optimized.cl
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m10820_a1-pure.cl
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m10820_a3-optimized.cl
…
m10820_a3-pure.cl
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m10830_a0-optimized.cl
…
m10830_a0-pure.cl
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m10830_a1-optimized.cl
…
m10830_a1-pure.cl
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m10830_a3-optimized.cl
…
m10830_a3-pure.cl
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m10840_a0-optimized.cl
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m10840_a0-pure.cl
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m10840_a1-optimized.cl
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m10840_a1-pure.cl
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m10840_a3-optimized.cl
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m10840_a3-pure.cl
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m10870_a0-optimized.cl
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m10870_a0-pure.cl
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m10870_a1-optimized.cl
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m10870_a1-pure.cl
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m10870_a3-optimized.cl
Update -m 10870 -a 3 function calls in optimized mode
2021-05-29 10:49:06 +02:00
m10870_a3-pure.cl
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m10900-pure.cl
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m11000_a0-optimized.cl
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m11000_a0-pure.cl
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m11000_a1-optimized.cl
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m11000_a1-pure.cl
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m11000_a3-optimized.cl
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m11000_a3-pure.cl
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m11100_a0-optimized.cl
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m11100_a0-pure.cl
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m11100_a1-optimized.cl
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m11100_a1-pure.cl
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m11100_a3-optimized.cl
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m11100_a3-pure.cl
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m11200_a0-optimized.cl
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m11200_a0-pure.cl
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m11200_a1-optimized.cl
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m11200_a1-pure.cl
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m11200_a3-optimized.cl
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m11200_a3-pure.cl
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m11300-pure.cl
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m11400_a0-pure.cl
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m11400_a1-pure.cl
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m11400_a3-pure.cl
…
m11500_a0-optimized.cl
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m11500_a1-optimized.cl
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m11500_a3-optimized.cl
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m11600-optimized.cl
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m11600-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m11700_a0-optimized.cl
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m11700_a0-pure.cl
…
m11700_a1-optimized.cl
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m11700_a1-pure.cl
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m11700_a3-optimized.cl
…
m11700_a3-pure.cl
…
m11750_a0-pure.cl
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m11750_a1-pure.cl
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m11750_a3-pure.cl
…
m11760_a0-pure.cl
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m11760_a1-pure.cl
…
m11760_a3-pure.cl
…
m11800_a0-optimized.cl
…
m11800_a0-pure.cl
…
m11800_a1-optimized.cl
…
m11800_a1-pure.cl
…
m11800_a3-optimized.cl
…
m11800_a3-pure.cl
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m11850_a0-pure.cl
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m11850_a1-pure.cl
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m11850_a3-pure.cl
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m11860_a0-pure.cl
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m11860_a1-pure.cl
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m11860_a3-pure.cl
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m11900-pure.cl
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m12000-pure.cl
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m12200-pure.cl
…
m12300-pure.cl
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m12400-pure.cl
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m12500-optimized.cl
…
m12500-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m12600_a0-optimized.cl
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m12600_a0-pure.cl
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m12600_a1-optimized.cl
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m12600_a1-pure.cl
…
m12600_a3-optimized.cl
…
m12600_a3-pure.cl
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m12700-pure.cl
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m12800-pure.cl
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m12900-pure.cl
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m13000-pure.cl
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m13100_a0-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a0-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a1-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a1-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a3-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a3-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13200-pure.cl
…
m13300_a0-optimized.cl
…
m13300_a0-pure.cl
…
m13300_a1-optimized.cl
…
m13300_a1-pure.cl
…
m13300_a3-optimized.cl
…
m13300_a3-pure.cl
…
m13400-pure.cl
KeePass: Increase supported size for KeePass 1 databases from 300kB to 16MB
2021-06-30 13:16:03 +02:00
m13500_a0-optimized.cl
…
m13500_a0-pure.cl
…
m13500_a1-optimized.cl
…
m13500_a1-pure.cl
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m13500_a3-optimized.cl
…
m13500_a3-pure.cl
…
m13600-pure.cl
WinZip Kernel: Increase supported data length from 8k to 16mb
2021-07-15 16:42:29 +02:00
m13711-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13712-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13713-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13721-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13722-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13723-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13731-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13732-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13733-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13751-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13752-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13753-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13771-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13772-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13773-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13800_a0-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a0-pure.cl
…
m13800_a1-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a1-pure.cl
…
m13800_a3-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a3-pure.cl
…
m13900_a0-optimized.cl
…
m13900_a0-pure.cl
…
m13900_a1-optimized.cl
…
m13900_a1-pure.cl
…
m13900_a3-optimized.cl
…
m13900_a3-pure.cl
…
m14000_a0-pure.cl
…
m14000_a1-pure.cl
…
m14000_a3-pure.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m14100_a0-pure.cl
…
m14100_a1-pure.cl
…
m14100_a3-pure.cl
…
m14400_a0-optimized.cl
…
m14400_a0-pure.cl
…
m14400_a1-optimized.cl
…
m14400_a1-pure.cl
…
m14400_a3-optimized.cl
…
m14400_a3-pure.cl
…
m14511_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14511_a1-pure.cl
…
m14511_a3-pure.cl
…
m14512_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14512_a1-pure.cl
…
m14512_a3-pure.cl
…
m14513_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14513_a1-pure.cl
…
m14513_a3-pure.cl
…
m14521_a0-pure.cl
…
m14521_a1-pure.cl
…
m14521_a3-pure.cl
…
m14522_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14522_a1-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14522_a3-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14523_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14523_a1-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14523_a3-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14531_a0-pure.cl
…
m14531_a1-pure.cl
…
m14531_a3-pure.cl
…
m14532_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14532_a1-pure.cl
…
m14532_a3-pure.cl
…
m14533_a0-pure.cl
…
m14533_a1-pure.cl
…
m14533_a3-pure.cl
…
m14541_a0-pure.cl
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m14541_a1-pure.cl
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m14541_a3-pure.cl
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m14542_a0-pure.cl
…
m14542_a1-pure.cl
…
m14542_a3-pure.cl
…
m14543_a0-pure.cl
…
m14543_a1-pure.cl
…
m14543_a3-pure.cl
…
m14551_a0-pure.cl
…
m14551_a1-pure.cl
…
m14551_a3-pure.cl
…
m14552_a0-pure.cl
…
m14552_a1-pure.cl
…
m14552_a3-pure.cl
…
m14553_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m14553_a1-pure.cl
…
m14553_a3-pure.cl
…
m14611-pure.cl
…
m14612-pure.cl
…
m14613-pure.cl
…
m14621-pure.cl
…
m14622-pure.cl
…
m14623-pure.cl
…
m14631-pure.cl
…
m14632-pure.cl
…
m14633-pure.cl
…
m14641-pure.cl
…
m14642-pure.cl
…
m14643-pure.cl
…
m14700-pure.cl
…
m14800-pure.cl
…
m14900_a0-optimized.cl
…
m14900_a1-optimized.cl
…
m14900_a3-optimized.cl
…
m15000_a0-optimized.cl
…
m15000_a0-pure.cl
…
m15000_a1-optimized.cl
…
m15000_a1-pure.cl
…
m15000_a3-optimized.cl
…
m15000_a3-pure.cl
…
m15100-pure.cl
…
m15300-pure.cl
…
m15400_a0-optimized.cl
…
m15400_a1-optimized.cl
…
m15400_a3-optimized.cl
…
m15500_a0-optimized.cl
…
m15500_a0-pure.cl
…
m15500_a1-optimized.cl
…
m15500_a1-pure.cl
…
m15500_a3-optimized.cl
…
m15500_a3-pure.cl
…
m15600-pure.cl
…
m15700-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m15900-pure.cl
Fixed false negative in hash-mode 15900 (DPAPI masterkey file v2) if password was longer than 64 characters.
2021-06-16 12:13:04 +02:00
m16000_a0-pure.cl
…
m16000_a1-pure.cl
…
m16000_a3-pure.cl
…
m16100_a0-optimized.cl
…
m16100_a0-pure.cl
…
m16100_a1-optimized.cl
…
m16100_a1-pure.cl
…
m16100_a3-optimized.cl
…
m16100_a3-pure.cl
…
m16200-pure.cl
…
m16300-pure.cl
…
m16400_a0-optimized.cl
…
m16400_a0-pure.cl
…
m16400_a1-optimized.cl
…
m16400_a1-pure.cl
…
m16400_a3-optimized.cl
…
m16400_a3-pure.cl
…
m16511_a0-pure.cl
…
m16511_a1-pure.cl
…
m16511_a3-pure.cl
…
m16512_a0-pure.cl
…
m16512_a1-pure.cl
…
m16512_a3-pure.cl
…
m16513_a0-pure.cl
…
m16513_a1-pure.cl
…
m16513_a3-pure.cl
…
m16600_a0-optimized.cl
…
m16600_a0-pure.cl
…
m16600_a1-optimized.cl
…
m16600_a1-pure.cl
…
m16600_a3-optimized.cl
…
m16600_a3-pure.cl
…
m16800-pure.cl
WPA Kernels: Increased performance by 3.5% for backend devices controlled by CUDA backend
2021-07-04 12:24:55 +02:00
m16801-pure.cl
…
m16900-pure.cl
…
m17200_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17200_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17200_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17300_a0-optimized.cl
…
m17300_a1-optimized.cl
…
m17300_a3-optimized.cl
…
m17400_a0-optimized.cl
…
m17400_a1-optimized.cl
…
m17400_a3-optimized.cl
…
m17500_a0-optimized.cl
…
m17500_a1-optimized.cl
…
m17500_a3-optimized.cl
…
m17600_a0-optimized.cl
…
m17600_a1-optimized.cl
…
m17600_a3-optimized.cl
…
m17700_a0-optimized.cl
…
m17700_a1-optimized.cl
…
m17700_a3-optimized.cl
…
m17800_a0-optimized.cl
…
m17800_a1-optimized.cl
…
m17800_a3-optimized.cl
…
m17900_a0-optimized.cl
…
m17900_a1-optimized.cl
…
m17900_a3-optimized.cl
…
m18000_a0-optimized.cl
…
m18000_a1-optimized.cl
…
m18000_a3-optimized.cl
…
m18100_a0-pure.cl
…
m18100_a1-pure.cl
…
m18100_a3-pure.cl
…
m18200_a0-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a0-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a1-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a1-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a3-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a3-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18300-pure.cl
…
m18400-pure.cl
…
m18500_a0-pure.cl
…
m18500_a1-pure.cl
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m18500_a3-pure.cl
…
m18600-pure.cl
Blowfish Kernels: Backport optimizations reducing bank conflicts from bcrypt to Password Safe v2 and Open Document Format (ODF) 1.1
2021-07-26 13:38:39 +02:00
m18700_a0-optimized.cl
…
m18700_a0-pure.cl
…
m18700_a1-optimized.cl
…
m18700_a1-pure.cl
…
m18700_a3-optimized.cl
…
m18700_a3-pure.cl
…
m18800-pure.cl
…
m18900-pure.cl
…
m19000-pure.cl
…
m19100-pure.cl
…
m19200-pure.cl
…
m19300_a0-pure.cl
…
m19300_a1-pure.cl
…
m19300_a3-pure.cl
…
m19500_a0-pure.cl
…
m19500_a1-pure.cl
…
m19500_a3-pure.cl
…
m19600-pure.cl
Fix variable declaration block level in -m 19600 and -m 19700
2021-07-13 22:22:53 +02:00
m19700-pure.cl
Fix variable declaration block level in -m 19600 and -m 19700
2021-07-13 22:22:53 +02:00
m19800-pure.cl
…
m19900-pure.cl
…
m20011-pure.cl
…
m20012-pure.cl
…
m20013-pure.cl
…
m20500_a0-pure.cl
…
m20500_a1-pure.cl
…
m20500_a3-pure.cl
…
m20510_a0-pure.cl
…
m20510_a1-pure.cl
…
m20510_a3-pure.cl
…
m20600-pure.cl
…
m20710_a0-optimized.cl
…
m20710_a0-pure.cl
…
m20710_a1-optimized.cl
…
m20710_a1-pure.cl
…
m20710_a3-optimized.cl
…
m20710_a3-pure.cl
…
m20720_a0-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m20720_a1-pure.cl
…
m20720_a3-pure.cl
…
m20800_a0-optimized.cl
…
m20800_a0-pure.cl
…
m20800_a1-optimized.cl
…
m20800_a1-pure.cl
…
m20800_a3-optimized.cl
…
m20800_a3-pure.cl
…
m20900_a0-optimized.cl
…
m20900_a0-pure.cl
…
m20900_a1-optimized.cl
…
m20900_a1-pure.cl
…
m20900_a3-optimized.cl
…
m20900_a3-pure.cl
…
m21000_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a0-pure.cl
…
m21000_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a1-pure.cl
…
m21000_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a3-pure.cl
…
m21100_a0-optimized.cl
…
m21100_a0-pure.cl
…
m21100_a1-optimized.cl
…
m21100_a1-pure.cl
…
m21100_a3-optimized.cl
…
m21100_a3-pure.cl
…
m21200_a0-optimized.cl
…
m21200_a0-pure.cl
…
m21200_a1-optimized.cl
…
m21200_a1-pure.cl
…
m21200_a3-optimized.cl
…
m21200_a3-pure.cl
…
m21300_a0-pure.cl
…
m21300_a1-pure.cl
…
m21300_a3-pure.cl
…
m21400_a0-optimized.cl
…
m21400_a0-pure.cl
…
m21400_a1-optimized.cl
…
m21400_a1-pure.cl
…
m21400_a3-optimized.cl
…
m21400_a3-pure.cl
…
m21500-pure.cl
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m21600-pure.cl
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m21700-pure.cl
…
m21800-pure.cl
…
m22000-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m22001-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m22100-pure.cl
…
m22200_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a0-pure.cl
…
m22200_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a1-pure.cl
…
m22200_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a3-pure.cl
…
m22300_a0-optimized.cl
…
m22300_a0-pure.cl
…
m22300_a1-optimized.cl
…
m22300_a1-pure.cl
…
m22300_a3-optimized.cl
…
m22300_a3-pure.cl
…
m22400-pure.cl
…
m22500_a0-optimized.cl
…
m22500_a0-pure.cl
…
m22500_a1-optimized.cl
…
m22500_a1-pure.cl
…
m22500_a3-optimized.cl
…
m22500_a3-pure.cl
…
m22600-pure.cl
…
m22700-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m22911_a0-pure.cl
…
m22911_a1-pure.cl
…
m22911_a3-pure.cl
…
m22921_a0-pure.cl
…
m22921_a1-pure.cl
…
m22921_a3-pure.cl
…
m22931_a0-pure.cl
…
m22931_a1-pure.cl
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m22931_a3-pure.cl
…
m22941_a0-pure.cl
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m22941_a1-pure.cl
…
m22941_a3-pure.cl
…
m22951_a0-pure.cl
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m22951_a1-pure.cl
…
m22951_a3-pure.cl
…
m23001_a0-optimized.cl
…
m23001_a0-pure.cl
…
m23001_a1-optimized.cl
…
m23001_a1-pure.cl
…
m23001_a3-optimized.cl
…
m23001_a3-pure.cl
…
m23002_a0-optimized.cl
…
m23002_a0-pure.cl
…
m23002_a1-optimized.cl
…
m23002_a1-pure.cl
…
m23002_a3-optimized.cl
…
m23002_a3-pure.cl
…
m23003_a0-optimized.cl
…
m23003_a0-pure.cl
…
m23003_a1-optimized.cl
…
m23003_a1-pure.cl
…
m23003_a3-optimized.cl
…
m23003_a3-pure.cl
…
m23100-pure.cl
…
m23200-pure.cl
…
m23300-pure.cl
…
m23400-pure.cl
…
m23500-pure.cl
…
m23600-pure.cl
…
m23700-optimized.cl
…
m23700-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m23800-optimized.cl
…
m23800-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m23900-pure.cl
…
m24100-pure.cl
…
m24200-pure.cl
…
m24300_a0-optimized.cl
…
m24300_a0-pure.cl
…
m24300_a1-optimized.cl
…
m24300_a1-pure.cl
…
m24300_a3-optimized.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m24300_a3-pure.cl
…
m24410-pure.cl
…
m24420-pure.cl
…
m24500-pure.cl
…
m24610-pure.cl
…
m24620-pure.cl
…
m24630-pure.cl
…
m24700_a0-optimized.cl
…
m24700_a0-pure.cl
…
m24700_a1-optimized.cl
…
m24700_a1-pure.cl
…
m24700_a3-optimized.cl
…
m24700_a3-pure.cl
…
m24800_a0-optimized.cl
…
m24800_a0-pure.cl
…
m24800_a1-optimized.cl
…
m24800_a1-pure.cl
…
m24800_a3-optimized.cl
…
m24800_a3-pure.cl
…
m24900_a0-optimized.cl
…
m24900_a1-optimized.cl
…
m24900_a3-optimized.cl
…
m25000-pure.cl
using shared buffer between md5 and sha1 SNMPV3_TMP_ELEMS_OPT, fix to crack real hashes
2021-07-26 22:25:15 +02:00
m25100-pure.cl
fix snmpv3 md5/sha1, tested with real hashes
2021-07-26 19:04:30 +02:00
m25200-pure.cl
fix snmpv3 md5/sha1, tested with real hashes
2021-07-26 19:04:30 +02:00
m25300-pure.cl
…
m25400-pure.cl
RC4 Kernels: Improved performance by 20%+ for hash-modes Kerberos 5 (etype 23), MS Office (<= 2003) and PDF (<= 1.6) by using new RC4 code
2021-05-31 08:28:13 +02:00
m25500-pure.cl
Unit-Tests: Added missing unit-test for Stargazer Stellar Wallet XLM
2021-06-10 09:02:26 +02:00
m25600-pure.cl
Fix password address space in m25600_init kernel
2021-07-07 10:35:41 +02:00
m25700_a0-optimized.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m25700_a1-optimized.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m25700_a3-optimized.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m25800-pure.cl
Bcrypt-SHA1/MD5 Kernels: Get rid of local memory use for binary to hex conversion to avoid false negatives on several OpenCL runtimes
2021-07-06 12:53:38 +02:00
m25900-pure.cl
minor whitespace fixes, per #2841
2021-06-21 07:47:22 -08:00
m26000_a0-pure.cl
update hash-mode to 26200
2021-06-05 00:10:17 +02:00
m26000_a1-pure.cl
update hash-mode to 26200
2021-06-05 00:10:17 +02:00
m26000_a3-pure.cl
update hash-mode to 26200
2021-06-05 00:10:17 +02:00
m26100-pure.cl
…
m26200_a0-pure.cl
minor whitespace fixes
2021-06-22 08:55:44 +02:00
m26200_a1-pure.cl
update hash-mode to 26200
2021-06-05 00:10:17 +02:00
m26200_a3-pure.cl
update hash-mode to 26200
2021-06-05 00:10:17 +02:00
m26300_a0-pure.cl
Renamed -m 7010 to -m 26300
2021-06-08 11:12:54 +02:00
m26300_a1-pure.cl
Renamed -m 7010 to -m 26300
2021-06-08 11:12:54 +02:00
m26300_a3-pure.cl
Renamed -m 7010 to -m 26300
2021-06-08 11:12:54 +02:00
m26401_a0-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26401_a1-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26401_a3-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26402_a0-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26402_a1-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26402_a3-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26403_a0-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26403_a1-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26403_a3-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26500-pure.cl
Added hash-mode: iPhone passcode (UID key + System Keybag)
2021-07-03 19:03:06 +02:00
m26600-pure.cl
add min/max data length limits to MetaMask Wallet
2021-07-04 20:14:25 +02:00
m26700-pure.cl
fix to crack real hashes
2021-07-26 22:45:02 +02:00
m26800-pure.cl
fix to crack real hashes
2021-07-26 23:00:33 +02:00
markov_be.cl
…
markov_le.cl
…
shared.cl
Implement gpu_bzero
2021-07-17 19:00:10 +03:00