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1b5168b95a2ab17c6795a26bbcd32609de48a4dc
hashcat/OpenCL
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Gabriele Gristina 1b5168b95a switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
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amp_a0.cl
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amp_a1.cl
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amp_a3.cl
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inc_cipher_aes.cl
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inc_cipher_aes.h
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inc_cipher_camellia.cl
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inc_cipher_camellia.h
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inc_cipher_des.cl
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inc_cipher_des.h
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inc_cipher_kuznyechik.cl
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inc_cipher_kuznyechik.h
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inc_cipher_serpent.cl
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inc_cipher_serpent.h
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inc_cipher_twofish.cl
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inc_cipher_twofish.h
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inc_common.cl
fix OpenCL compiler warning
2019-06-21 21:26:42 +02:00
inc_common.h
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inc_comp_multi_bs.cl
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inc_comp_multi_bs.h
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inc_comp_multi.cl
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inc_comp_multi.h
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inc_comp_single_bs.cl
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inc_comp_single_bs.h
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inc_comp_single.cl
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inc_comp_single.h
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inc_diskcryptor_xts.cl
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inc_diskcryptor_xts.h
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inc_hash_md4.cl
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inc_hash_md4.h
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inc_hash_md5.cl
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inc_hash_md5.h
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inc_hash_ripemd160.cl
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inc_hash_ripemd160.h
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inc_hash_sha1.cl
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inc_hash_sha1.h
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inc_hash_sha224.cl
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inc_hash_sha224.h
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inc_hash_sha256.cl
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inc_hash_sha256.h
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inc_hash_sha384.cl
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inc_hash_sha384.h
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inc_hash_sha512.cl
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inc_hash_sha512.h
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inc_hash_streebog256.cl
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inc_hash_streebog256.h
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inc_hash_streebog512.cl
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inc_hash_streebog512.h
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inc_hash_whirlpool.cl
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inc_hash_whirlpool.h
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inc_luks_aes.cl
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inc_luks_aes.h
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inc_luks_af.cl
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inc_luks_af.h
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inc_luks_essiv.cl
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inc_luks_essiv.h
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inc_luks_serpent.cl
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inc_luks_serpent.h
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inc_luks_twofish.cl
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inc_luks_twofish.h
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inc_luks_xts.cl
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inc_luks_xts.h
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inc_platform.cl
Some more ROCm performance tuning
2019-06-20 10:04:31 +02:00
inc_platform.h
Some more ROCm performance tuning
2019-06-20 10:04:31 +02:00
inc_rp_optimized.cl
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inc_rp_optimized.h
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inc_rp.cl
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inc_rp.h
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inc_scalar.cl
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inc_scalar.h
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inc_simd.cl
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inc_simd.h
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inc_truecrypt_crc32.cl
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inc_truecrypt_crc32.h
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inc_truecrypt_keyfile.cl
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inc_truecrypt_keyfile.h
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inc_truecrypt_xts.cl
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inc_truecrypt_xts.h
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inc_types.h
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inc_vendor.h
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inc_veracrypt_xts.cl
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inc_veracrypt_xts.h
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inc_zip_inflate.cl
pkzip: some more missing DECLSPEC found
2019-06-07 20:14:15 +02:00
m00000_a0-optimized.cl
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m03100_a0-optimized.cl
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m03100_a1-optimized.cl
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m03100_a3-optimized.cl
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m03200-pure.cl
Use __launch_bounds__ in CUDA as replacement for reqd_work_group_size() in OpenCL
2019-06-16 18:01:26 +02:00
m03710_a0-optimized.cl
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m07700_a0-optimized.cl
Some more ROCm performance tuning for -m 77xx
2019-06-20 16:16:56 +02:00
m07700_a1-optimized.cl
Some more ROCm performance tuning for -m 77xx
2019-06-20 16:16:56 +02:00
m07700_a3-optimized.cl
Some more ROCm performance tuning for -m 77xx
2019-06-20 16:16:56 +02:00
m07701_a0-optimized.cl
Some more ROCm performance tuning for -m 77xx
2019-06-20 16:16:56 +02:00
m07701_a1-optimized.cl
Some more ROCm performance tuning for -m 77xx
2019-06-20 16:16:56 +02:00
m07701_a3-optimized.cl
Some more ROCm performance tuning for -m 77xx
2019-06-20 16:16:56 +02:00
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m08500_a0-pure.cl
…
m08500_a1-pure.cl
…
m08500_a3-pure.cl
…
m08600_a0-pure.cl
…
m08600_a1-pure.cl
…
m08600_a3-pure.cl
…
m08700_a0-optimized.cl
…
m08700_a1-optimized.cl
…
m08700_a3-optimized.cl
…
m08800-pure.cl
…
m08900-pure.cl
…
m09000-pure.cl
Use __launch_bounds__ in CUDA as replacement for reqd_work_group_size() in OpenCL
2019-06-16 18:01:26 +02:00
m09100-pure.cl
…
m09400-pure.cl
…
m09500-pure.cl
…
m09600-pure.cl
…
m09700_a0-optimized.cl
…
m09700_a1-optimized.cl
…
m09700_a3-optimized.cl
Get rid of m08, m16, s08, s16 kernels in -m 9700 and -m 9720 since maximum password length for old office documents is 15
2019-06-04 17:01:35 +02:00
m09710_a0-optimized.cl
…
m09710_a1-optimized.cl
…
m09710_a3-optimized.cl
…
m09720_a0-optimized.cl
…
m09720_a1-optimized.cl
…
m09720_a3-optimized.cl
Get rid of m08, m16, s08, s16 kernels in -m 9700 and -m 9720 since maximum password length for old office documents is 15
2019-06-04 17:01:35 +02:00
m09800_a0-optimized.cl
…
m09800_a1-optimized.cl
…
m09800_a3-optimized.cl
…
m09810_a0-optimized.cl
…
m09810_a1-optimized.cl
…
m09810_a3-optimized.cl
…
m09820_a0-optimized.cl
…
m09820_a1-optimized.cl
…
m09820_a3-optimized.cl
…
m09900_a0-optimized.cl
…
m09900_a0-pure.cl
…
m09900_a1-optimized.cl
…
m09900_a1-pure.cl
…
m09900_a3-optimized.cl
…
m09900_a3-pure.cl
…
m10100_a0-optimized.cl
…
m10100_a1-optimized.cl
…
m10100_a3-optimized.cl
…
m10300-pure.cl
…
m10400_a0-optimized.cl
…
m10400_a1-optimized.cl
…
m10400_a3-optimized.cl
…
m10410_a0-optimized.cl
…
m10410_a1-optimized.cl
…
m10410_a3-optimized.cl
…
m10420_a0-optimized.cl
…
m10420_a1-optimized.cl
…
m10420_a3-optimized.cl
…
m10500-pure.cl
…
m10700-optimized.cl
…
m10700-pure.cl
…
m10800_a0-optimized.cl
…
m10800_a0-pure.cl
…
m10800_a1-optimized.cl
…
m10800_a1-pure.cl
…
m10800_a3-optimized.cl
…
m10800_a3-pure.cl
…
m10900-pure.cl
…
m11000_a0-optimized.cl
…
m11000_a0-pure.cl
…
m11000_a1-optimized.cl
…
m11000_a1-pure.cl
…
m11000_a3-optimized.cl
…
m11000_a3-pure.cl
…
m11100_a0-optimized.cl
…
m11100_a0-pure.cl
…
m11100_a1-optimized.cl
…
m11100_a1-pure.cl
…
m11100_a3-optimized.cl
…
m11100_a3-pure.cl
…
m11200_a0-optimized.cl
…
m11200_a0-pure.cl
…
m11200_a1-optimized.cl
…
m11200_a1-pure.cl
…
m11200_a3-optimized.cl
…
m11200_a3-pure.cl
…
m11300-pure.cl
…
m11400_a0-pure.cl
…
m11400_a1-pure.cl
…
m11400_a3-pure.cl
…
m11500_a0-optimized.cl
Speed up -m 11500 in general
2019-06-04 12:15:34 +02:00
m11500_a1-optimized.cl
Speed up -m 11500 in general
2019-06-04 12:15:34 +02:00
m11500_a3-optimized.cl
Speed up -m 11500 in general
2019-06-04 12:15:34 +02:00
m11600-pure.cl
…
m11700_a0-optimized.cl
…
m11700_a0-pure.cl
…
m11700_a1-optimized.cl
…
m11700_a1-pure.cl
…
m11700_a3-optimized.cl
…
m11700_a3-pure.cl
…
m11750_a0-pure.cl
…
m11750_a1-pure.cl
…
m11750_a3-pure.cl
…
m11760_a0-pure.cl
…
m11760_a1-pure.cl
…
m11760_a3-pure.cl
…
m11800_a0-optimized.cl
…
m11800_a0-pure.cl
…
m11800_a1-optimized.cl
…
m11800_a1-pure.cl
…
m11800_a3-optimized.cl
…
m11800_a3-pure.cl
…
m11850_a0-pure.cl
…
m11850_a1-pure.cl
…
m11850_a3-pure.cl
…
m11860_a0-pure.cl
…
m11860_a1-pure.cl
…
m11860_a3-pure.cl
…
m11900-pure.cl
…
m12000-pure.cl
…
m12200-pure.cl
…
m12300-pure.cl
…
m12400-pure.cl
…
m12500-pure.cl
…
m12600_a0-optimized.cl
…
m12600_a0-pure.cl
…
m12600_a1-optimized.cl
…
m12600_a1-pure.cl
…
m12600_a3-optimized.cl
…
m12600_a3-pure.cl
…
m12700-pure.cl
…
m12800-pure.cl
…
m12900-pure.cl
…
m13000-pure.cl
…
m13100_a0-optimized.cl
…
m13100_a0-pure.cl
…
m13100_a1-optimized.cl
…
m13100_a1-pure.cl
…
m13100_a3-optimized.cl
…
m13100_a3-pure.cl
…
m13200-pure.cl
…
m13300_a0-optimized.cl
…
m13300_a0-pure.cl
…
m13300_a1-optimized.cl
…
m13300_a1-pure.cl
…
m13300_a3-optimized.cl
…
m13300_a3-pure.cl
…
m13400-pure.cl
…
m13500_a0-optimized.cl
…
m13500_a0-pure.cl
…
m13500_a1-optimized.cl
…
m13500_a1-pure.cl
…
m13500_a3-optimized.cl
…
m13500_a3-pure.cl
…
m13600-pure.cl
WipZip cracking: Added two byte early reject, resulting in higher cracking speed
2019-06-16 11:41:42 +02:00
m13711-pure.cl
…
m13712-pure.cl
…
m13713-pure.cl
…
m13721-pure.cl
…
m13722-pure.cl
…
m13723-pure.cl
…
m13731-pure.cl
…
m13732-pure.cl
…
m13733-pure.cl
…
m13751-pure.cl
…
m13752-pure.cl
…
m13753-pure.cl
…
m13771-pure.cl
…
m13772-pure.cl
…
m13773-pure.cl
…
m13800_a0-optimized.cl
…
m13800_a0-pure.cl
…
m13800_a1-optimized.cl
…
m13800_a1-pure.cl
…
m13800_a3-optimized.cl
…
m13800_a3-pure.cl
…
m13900_a0-optimized.cl
…
m13900_a0-pure.cl
…
m13900_a1-optimized.cl
…
m13900_a1-pure.cl
…
m13900_a3-optimized.cl
…
m13900_a3-pure.cl
…
m14000_a0-pure.cl
…
m14000_a1-pure.cl
…
m14000_a3-pure.cl
…
m14100_a0-pure.cl
…
m14100_a1-pure.cl
…
m14100_a3-pure.cl
…
m14400_a0-optimized.cl
…
m14400_a0-pure.cl
…
m14400_a1-optimized.cl
…
m14400_a1-pure.cl
…
m14400_a3-optimized.cl
…
m14400_a3-pure.cl
…
m14611-pure.cl
…
m14612-pure.cl
…
m14613-pure.cl
…
m14621-pure.cl
…
m14622-pure.cl
…
m14623-pure.cl
…
m14631-pure.cl
…
m14632-pure.cl
…
m14633-pure.cl
…
m14641-pure.cl
…
m14642-pure.cl
…
m14643-pure.cl
…
m14700-pure.cl
…
m14800-pure.cl
…
m14900_a0-optimized.cl
…
m14900_a1-optimized.cl
…
m14900_a3-optimized.cl
…
m15000_a0-optimized.cl
…
m15000_a0-pure.cl
…
m15000_a1-optimized.cl
…
m15000_a1-pure.cl
…
m15000_a3-optimized.cl
Speed up -m 15000 in optimized -a 3 mode
2019-06-04 10:52:28 +02:00
m15000_a3-pure.cl
…
m15100-pure.cl
…
m15300-pure.cl
…
m15400_a0-optimized.cl
…
m15400_a1-optimized.cl
…
m15400_a3-optimized.cl
Fix -m 16100 in optimized -a 3 mode
2019-06-04 11:20:32 +02:00
m15500_a0-optimized.cl
…
m15500_a0-pure.cl
…
m15500_a1-optimized.cl
…
m15500_a1-pure.cl
…
m15500_a3-optimized.cl
…
m15500_a3-pure.cl
…
m15600-pure.cl
…
m15700-pure.cl
…
m15900-pure.cl
…
m16000_a0-pure.cl
…
m16000_a1-pure.cl
…
m16000_a3-pure.cl
…
m16100_a0-optimized.cl
…
m16100_a0-pure.cl
…
m16100_a1-optimized.cl
…
m16100_a1-pure.cl
…
m16100_a3-optimized.cl
…
m16100_a3-pure.cl
…
m16200-pure.cl
…
m16300-pure.cl
…
m16400_a0-optimized.cl
…
m16400_a0-pure.cl
…
m16400_a1-optimized.cl
…
m16400_a1-pure.cl
…
m16400_a3-optimized.cl
…
m16400_a3-pure.cl
…
m16511_a0-pure.cl
…
m16511_a1-pure.cl
…
m16511_a3-pure.cl
…
m16512_a0-pure.cl
…
m16512_a1-pure.cl
…
m16512_a3-pure.cl
…
m16513_a0-pure.cl
…
m16513_a1-pure.cl
…
m16513_a3-pure.cl
…
m16600_a0-optimized.cl
Merge pull request #2021 from philsmd/master
2019-05-14 11:57:46 +02:00
m16600_a0-pure.cl
Merge pull request #2021 from philsmd/master
2019-05-14 11:57:46 +02:00
m16600_a1-optimized.cl
Merge pull request #2021 from philsmd/master
2019-05-14 11:57:46 +02:00
m16600_a1-pure.cl
Merge pull request #2021 from philsmd/master
2019-05-14 11:57:46 +02:00
m16600_a3-optimized.cl
Merge pull request #2021 from philsmd/master
2019-05-14 11:57:46 +02:00
m16600_a3-pure.cl
Merge pull request #2021 from philsmd/master
2019-05-14 11:57:46 +02:00
m16800-pure.cl
…
m16801-pure.cl
…
m16900-pure.cl
…
m17200_a0-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17200_a1-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17200_a3-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17210_a0-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17210_a1-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17210_a3-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17220_a0-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17220_a1-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17220_a3-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17225_a0-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17225_a1-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17225_a3-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17230_a0-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17230_a1-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17230_a3-pure.cl
pkzip: for u32 use MAX_DATA / 4
2019-06-07 19:42:28 +02:00
m17300_a0-optimized.cl
…
m17300_a1-optimized.cl
…
m17300_a3-optimized.cl
…
m17400_a0-optimized.cl
…
m17400_a1-optimized.cl
…
m17400_a3-optimized.cl
…
m17500_a0-optimized.cl
…
m17500_a1-optimized.cl
…
m17500_a3-optimized.cl
…
m17600_a0-optimized.cl
…
m17600_a1-optimized.cl
…
m17600_a3-optimized.cl
…
m17700_a0-optimized.cl
…
m17700_a1-optimized.cl
…
m17700_a3-optimized.cl
…
m17800_a0-optimized.cl
…
m17800_a1-optimized.cl
…
m17800_a3-optimized.cl
…
m17900_a0-optimized.cl
…
m17900_a1-optimized.cl
…
m17900_a3-optimized.cl
…
m18000_a0-optimized.cl
…
m18000_a1-optimized.cl
…
m18000_a3-optimized.cl
…
m18100_a0-pure.cl
…
m18100_a1-pure.cl
…
m18100_a3-pure.cl
…
m18200_a0-optimized.cl
…
m18200_a0-pure.cl
…
m18200_a1-optimized.cl
…
m18200_a1-pure.cl
…
m18200_a3-optimized.cl
…
m18200_a3-pure.cl
…
m18300-pure.cl
…
m18400-pure.cl
…
m18500_a0-pure.cl
…
m18500_a1-pure.cl
…
m18500_a3-pure.cl
…
m18600-pure.cl
Use __launch_bounds__ in CUDA as replacement for reqd_work_group_size() in OpenCL
2019-06-16 18:01:26 +02:00
m18700_a0-optimized.cl
…
m18700_a0-pure.cl
…
m18700_a1-optimized.cl
…
m18700_a1-pure.cl
…
m18700_a3-optimized.cl
…
m18700_a3-pure.cl
…
m18800-pure.cl
…
m18900-pure.cl
…
m19000-pure.cl
…
m19100-pure.cl
…
m19200-pure.cl
…
m19300_a0-pure.cl
Speed up -m 19300 in general
2019-06-06 15:02:22 +02:00
m19300_a1-pure.cl
Speed up -m 19300 in general
2019-06-06 15:02:22 +02:00
m19300_a3-pure.cl
Speed up -m 19300 in general
2019-06-06 15:02:22 +02:00
m19500_a0-pure.cl
…
m19500_a1-pure.cl
…
m19500_a3-pure.cl
…
m19600-pure.cl
…
m19700-pure.cl
…
m19800-pure.cl
…
m19900-pure.cl
…
m20011-pure.cl
…
m20012-pure.cl
…
m20013-pure.cl
…
m20500_a0-pure.cl
minor: some code formatting changes for PKZIP
2019-06-07 17:24:13 +02:00
m20500_a1-pure.cl
minor: some code formatting changes for PKZIP
2019-06-07 17:24:13 +02:00
m20500_a3-pure.cl
minor: some code formatting changes for PKZIP
2019-06-07 17:24:13 +02:00
m20510_a0-pure.cl
minor: some code formatting changes for PKZIP
2019-06-07 17:24:13 +02:00
m20510_a1-pure.cl
minor: some code formatting changes for PKZIP
2019-06-07 17:24:13 +02:00
m20510_a3-pure.cl
minor: some code formatting changes for PKZIP
2019-06-07 17:24:13 +02:00
m20600-pure.cl
add hash mode 20600 (oracle transportation manager)
2019-06-18 11:41:41 -05:00
m20900_a0-optimized.cl
switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
m20900_a0-pure.cl
switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
m20900_a1-optimized.cl
switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
m20900_a1-pure.cl
switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
m20900_a3-optimized.cl
switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
m20900_a3-pure.cl
switch hash-mode from 4410 to 20900
2019-07-30 15:08:55 +02:00
markov_be.cl
…
markov_le.cl
…