DeforaNetworks/hashcat
3
0
Fork 0
Code Releases Activity
Files
089a4847dbc823bb746575b131f328b4117bde3b
hashcat/OpenCL
T
History
Jens Steube f9f3d5bbd8 Merge pull request #2924 from matrix/snmpv3_opts_if 
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-04 21:06:11 +02:00
..
amp_a0.cl
…
amp_a1.cl
…
amp_a3.cl
…
inc_cipher_aes-gcm.cl
add min/max data length limits to MetaMask Wallet
2021-07-04 20:14:25 +02:00
inc_cipher_aes-gcm.h
…
inc_cipher_aes.cl
…
inc_cipher_aes.h
…
inc_cipher_camellia.cl
…
inc_cipher_camellia.h
…
inc_cipher_des.cl
…
inc_cipher_des.h
…
inc_cipher_kuznyechik.cl
…
inc_cipher_kuznyechik.h
…
inc_cipher_rc4.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
inc_cipher_rc4.h
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
inc_cipher_serpent.cl
…
inc_cipher_serpent.h
…
inc_cipher_twofish.cl
…
inc_cipher_twofish.h
…
inc_common.cl
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
inc_common.h
Add missing backports from code base v6.2.2
2021-07-11 12:38:59 +02:00
inc_comp_multi_bs.cl
…
inc_comp_multi_bs.h
…
inc_comp_multi.cl
…
inc_comp_multi.h
…
inc_comp_single_bs.cl
…
inc_comp_single_bs.h
…
inc_comp_single.cl
…
inc_comp_single.h
…
inc_diskcryptor_xts.cl
…
inc_diskcryptor_xts.h
…
inc_ecc_secp256k1.cl
AMD GPUs: On Apple OpenCL platform, we ask for the preferred kernel thread size rather than hard-coding 32
2021-07-27 09:37:31 +02:00
inc_ecc_secp256k1.h
…
inc_hash_blake2b.cl
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
inc_hash_blake2b.h
Optimize BLAKE2B_ROUND() 64 bit rotates
2021-07-17 18:18:22 +02:00
inc_hash_md4.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_md4.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_md5.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_md5.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_ripemd160.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_ripemd160.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha1.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha1.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha224.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha224.h
…
inc_hash_sha256.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha256.h
…
inc_hash_sha384.cl
Fixed datatype in function sha384_hmac_init_vector_128() that could come into effect if vector datatype was manually set
2021-07-19 15:58:38 +02:00
inc_hash_sha384.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_sha512.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_sha512.h
Revert adding make_u32x() for constants to crypto primitives, fails on OpenCL
2021-07-20 10:34:34 +02:00
inc_hash_streebog256.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_streebog256.h
…
inc_hash_streebog512.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_streebog512.h
…
inc_hash_whirlpool.cl
OpenCL Runtime: Workaround a problem of the AMD OpenCL GPU driver under macOS which results in false negatives due to changes in the kernel crypto library
2021-07-05 11:33:12 +02:00
inc_hash_whirlpool.h
…
inc_luks_aes.cl
…
inc_luks_aes.h
…
inc_luks_af.cl
…
inc_luks_af.h
…
inc_luks_essiv.cl
…
inc_luks_essiv.h
…
inc_luks_serpent.cl
…
inc_luks_serpent.h
…
inc_luks_twofish.cl
…
inc_luks_twofish.h
…
inc_luks_xts.cl
…
inc_luks_xts.h
…
inc_platform.cl
Update module_unstable_warning() for -m 172xx on HIP
2021-07-23 21:09:55 +02:00
inc_platform.h
Switch HIP vector datatypes to OpenCL like ext_vector_type()
2021-07-19 20:24:30 +02:00
inc_rp_optimized.cl
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp_optimized.h
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp.cl
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_rp.h
Add new rule function '3' to switch the case of the first letter after occurrence N of char X
2021-08-01 00:04:10 +02:00
inc_scalar.cl
…
inc_scalar.h
…
inc_simd.cl
…
inc_simd.h
Fixed false negative in all VeraCrypt hash-modes if both conditions are met: 1. use CPU for cracking and 2. PIM range was used
2021-07-20 11:31:31 +02:00
inc_truecrypt_crc32.cl
…
inc_truecrypt_crc32.h
…
inc_truecrypt_keyfile.cl
…
inc_truecrypt_keyfile.h
…
inc_truecrypt_xts.cl
…
inc_truecrypt_xts.h
…
inc_types.h
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
inc_vendor.h
Work around segmentation fault in Intel JiT 2021.12.6.0.19_160000 compiling hc_enc_next()/hc_enc_next_global()
2021-08-03 08:34:37 +02:00
inc_veracrypt_keyfile.cl
…
inc_veracrypt_keyfile.h
…
inc_veracrypt_xts.cl
…
inc_veracrypt_xts.h
…
inc_zip_inflate.cl
Add missing u64 vector datatypes mapping for OpenCL
2021-07-27 09:54:15 +02:00
m00000_a0-optimized.cl
…
m00000_a0-pure.cl
…
m00000_a1-optimized.cl
…
m00000_a1-pure.cl
…
m00000_a3-optimized.cl
…
m00000_a3-pure.cl
…
m00010_a0-optimized.cl
…
m00010_a0-pure.cl
…
m00010_a1-optimized.cl
…
m00010_a1-pure.cl
…
m00010_a3-optimized.cl
…
m00010_a3-pure.cl
…
m00020_a0-optimized.cl
…
m00020_a0-pure.cl
…
m00020_a1-optimized.cl
…
m00020_a1-pure.cl
…
m00020_a3-optimized.cl
…
m00020_a3-pure.cl
…
m00030_a0-optimized.cl
…
m00030_a0-pure.cl
…
m00030_a1-optimized.cl
…
m00030_a1-pure.cl
…
m00030_a3-optimized.cl
…
m00030_a3-pure.cl
…
m00040_a0-optimized.cl
…
m00040_a0-pure.cl
…
m00040_a1-optimized.cl
…
m00040_a1-pure.cl
…
m00040_a3-optimized.cl
…
m00040_a3-pure.cl
…
m00050_a0-optimized.cl
…
m00050_a0-pure.cl
…
m00050_a1-optimized.cl
…
m00050_a1-pure.cl
…
m00050_a3-optimized.cl
…
m00050_a3-pure.cl
…
m00060_a0-optimized.cl
…
m00060_a0-pure.cl
…
m00060_a1-optimized.cl
…
m00060_a1-pure.cl
…
m00060_a3-optimized.cl
…
m00060_a3-pure.cl
…
m00070_a0-optimized.cl
…
m00070_a0-pure.cl
…
m00070_a1-optimized.cl
…
m00070_a1-pure.cl
…
m00070_a3-optimized.cl
…
m00070_a3-pure.cl
…
m00100_a0-optimized.cl
…
m00100_a0-pure.cl
…
m00100_a1-optimized.cl
…
m00100_a1-pure.cl
…
m00100_a3-optimized.cl
…
m00100_a3-pure.cl
…
m00110_a0-optimized.cl
…
m00110_a0-pure.cl
…
m00110_a1-optimized.cl
…
m00110_a1-pure.cl
…
m00110_a3-optimized.cl
…
m00110_a3-pure.cl
…
m00120_a0-optimized.cl
…
m00120_a0-pure.cl
…
m00120_a1-optimized.cl
…
m00120_a1-pure.cl
…
m00120_a3-optimized.cl
…
m00120_a3-pure.cl
…
m00130_a0-optimized.cl
…
m00130_a0-pure.cl
…
m00130_a1-optimized.cl
…
m00130_a1-pure.cl
…
m00130_a3-optimized.cl
…
m00130_a3-pure.cl
…
m00140_a0-optimized.cl
…
m00140_a0-pure.cl
…
m00140_a1-optimized.cl
…
m00140_a1-pure.cl
…
m00140_a3-optimized.cl
…
m00140_a3-pure.cl
…
m00150_a0-optimized.cl
…
m00150_a0-pure.cl
…
m00150_a1-optimized.cl
…
m00150_a1-pure.cl
…
m00150_a3-optimized.cl
…
m00150_a3-pure.cl
…
m00160_a0-optimized.cl
…
m00160_a0-pure.cl
…
m00160_a1-optimized.cl
…
m00160_a1-pure.cl
…
m00160_a3-optimized.cl
…
m00160_a3-pure.cl
…
m00170_a0-optimized.cl
…
m00170_a0-pure.cl
…
m00170_a1-optimized.cl
…
m00170_a1-pure.cl
…
m00170_a3-optimized.cl
…
m00170_a3-pure.cl
…
m00200_a0-optimized.cl
…
m00200_a1-optimized.cl
…
m00200_a3-optimized.cl
…
m00300_a0-optimized.cl
…
m00300_a0-pure.cl
…
m00300_a1-optimized.cl
…
m00300_a1-pure.cl
…
m00300_a3-optimized.cl
…
m00300_a3-pure.cl
…
m00400-optimized.cl
…
m00400-pure.cl
…
m00500-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m00500-pure.cl
…
m00600_a0-optimized.cl
…
m00600_a0-pure.cl
…
m00600_a1-optimized.cl
…
m00600_a1-pure.cl
…
m00600_a3-optimized.cl
…
m00600_a3-pure.cl
…
m00900_a0-optimized.cl
…
m00900_a0-pure.cl
…
m00900_a1-optimized.cl
…
m00900_a1-pure.cl
…
m00900_a3-optimized.cl
…
m00900_a3-pure.cl
…
m01000_a0-optimized.cl
…
m01000_a0-pure.cl
…
m01000_a1-optimized.cl
…
m01000_a1-pure.cl
…
m01000_a3-optimized.cl
…
m01000_a3-pure.cl
…
m01100_a0-optimized.cl
…
m01100_a0-pure.cl
…
m01100_a1-optimized.cl
…
m01100_a1-pure.cl
…
m01100_a3-optimized.cl
…
m01100_a3-pure.cl
…
m01300_a0-optimized.cl
…
m01300_a0-pure.cl
…
m01300_a1-optimized.cl
…
m01300_a1-pure.cl
…
m01300_a3-optimized.cl
…
m01300_a3-pure.cl
…
m01400_a0-optimized.cl
…
m01400_a0-pure.cl
…
m01400_a1-optimized.cl
…
m01400_a1-pure.cl
…
m01400_a3-optimized.cl
…
m01400_a3-pure.cl
…
m01410_a0-optimized.cl
…
m01410_a0-pure.cl
…
m01410_a1-optimized.cl
…
m01410_a1-pure.cl
…
m01410_a3-optimized.cl
…
m01410_a3-pure.cl
…
m01420_a0-optimized.cl
…
m01420_a0-pure.cl
…
m01420_a1-optimized.cl
…
m01420_a1-pure.cl
…
m01420_a3-optimized.cl
…
m01420_a3-pure.cl
…
m01430_a0-optimized.cl
…
m01430_a0-pure.cl
…
m01430_a1-optimized.cl
…
m01430_a1-pure.cl
…
m01430_a3-optimized.cl
…
m01430_a3-pure.cl
…
m01440_a0-optimized.cl
…
m01440_a0-pure.cl
…
m01440_a1-optimized.cl
…
m01440_a1-pure.cl
…
m01440_a3-optimized.cl
…
m01440_a3-pure.cl
…
m01450_a0-optimized.cl
…
m01450_a0-pure.cl
…
m01450_a1-optimized.cl
…
m01450_a1-pure.cl
…
m01450_a3-optimized.cl
…
m01450_a3-pure.cl
…
m01460_a0-optimized.cl
…
m01460_a0-pure.cl
…
m01460_a1-optimized.cl
…
m01460_a1-pure.cl
…
m01460_a3-optimized.cl
…
m01460_a3-pure.cl
…
m01470_a0-optimized.cl
…
m01470_a0-pure.cl
…
m01470_a1-optimized.cl
…
m01470_a1-pure.cl
…
m01470_a3-optimized.cl
…
m01470_a3-pure.cl
…
m01500_a0-pure.cl
…
m01500_a1-pure.cl
…
m01500_a3-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m01600-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m01600-pure.cl
…
m01700_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a0-pure.cl
…
m01700_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a1-pure.cl
…
m01700_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01700_a3-pure.cl
…
m01710_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a0-pure.cl
…
m01710_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a1-pure.cl
…
m01710_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01710_a3-pure.cl
…
m01720_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a0-pure.cl
…
m01720_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a1-pure.cl
…
m01720_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01720_a3-pure.cl
…
m01730_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a0-pure.cl
…
m01730_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a1-pure.cl
…
m01730_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01730_a3-pure.cl
…
m01740_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a0-pure.cl
…
m01740_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a1-pure.cl
…
m01740_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m01740_a3-pure.cl
…
m01750_a0-optimized.cl
…
m01750_a0-pure.cl
…
m01750_a1-optimized.cl
…
m01750_a1-pure.cl
…
m01750_a3-optimized.cl
…
m01750_a3-pure.cl
…
m01760_a0-optimized.cl
…
m01760_a0-pure.cl
…
m01760_a1-optimized.cl
…
m01760_a1-pure.cl
…
m01760_a3-optimized.cl
…
m01760_a3-pure.cl
…
m01770_a0-optimized.cl
…
m01770_a0-pure.cl
…
m01770_a1-optimized.cl
…
m01770_a1-pure.cl
…
m01770_a3-optimized.cl
…
m01770_a3-pure.cl
…
m01800-optimized.cl
…
m01800-pure.cl
…
m02000_a0-optimized.cl
…
m02000_a0-pure.cl
…
m02000_a1-optimized.cl
…
m02000_a1-pure.cl
…
m02000_a3-optimized.cl
…
m02000_a3-pure.cl
…
m02100-pure.cl
…
m02400_a0-optimized.cl
…
m02400_a1-optimized.cl
…
m02400_a3-optimized.cl
…
m02410_a0-optimized.cl
…
m02410_a1-optimized.cl
…
m02410_a3-optimized.cl
…
m02500-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m02501-pure.cl
…
m02610_a0-optimized.cl
…
m02610_a0-pure.cl
…
m02610_a1-optimized.cl
…
m02610_a1-pure.cl
…
m02610_a3-optimized.cl
…
m02610_a3-pure.cl
…
m02710_a0-optimized.cl
…
m02710_a1-optimized.cl
…
m02710_a3-optimized.cl
…
m02810_a0-optimized.cl
…
m02810_a0-pure.cl
…
m02810_a1-optimized.cl
…
m02810_a1-pure.cl
…
m02810_a3-optimized.cl
…
m02810_a3-pure.cl
…
m03000_a0-pure.cl
…
m03000_a1-pure.cl
…
m03000_a3-pure.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m03100_a0-optimized.cl
…
m03100_a1-optimized.cl
…
m03100_a3-optimized.cl
…
m03200-pure.cl
…
m03500_a0-optimized.cl
…
m03500_a0-pure.cl
…
m03500_a1-optimized.cl
…
m03500_a1-pure.cl
…
m03500_a3-optimized.cl
…
m03500_a3-pure.cl
…
m03710_a0-optimized.cl
…
m03710_a0-pure.cl
…
m03710_a1-optimized.cl
…
m03710_a1-pure.cl
…
m03710_a3-optimized.cl
…
m03710_a3-pure.cl
…
m03800_a0-optimized.cl
…
m03800_a0-pure.cl
…
m03800_a1-optimized.cl
…
m03800_a1-pure.cl
…
m03800_a3-optimized.cl
…
m03800_a3-pure.cl
…
m03910_a0-optimized.cl
…
m03910_a0-pure.cl
…
m03910_a1-optimized.cl
…
m03910_a1-pure.cl
…
m03910_a3-optimized.cl
…
m03910_a3-pure.cl
…
m04010_a0-optimized.cl
…
m04010_a0-pure.cl
…
m04010_a1-optimized.cl
…
m04010_a1-pure.cl
…
m04010_a3-optimized.cl
…
m04010_a3-pure.cl
…
m04110_a0-optimized.cl
…
m04110_a0-pure.cl
…
m04110_a1-optimized.cl
…
m04110_a1-pure.cl
…
m04110_a3-optimized.cl
…
m04110_a3-pure.cl
…
m04310_a0-optimized.cl
…
m04310_a0-pure.cl
…
m04310_a1-optimized.cl
…
m04310_a1-pure.cl
…
m04310_a3-optimized.cl
…
m04310_a3-pure.cl
…
m04400_a0-optimized.cl
…
m04400_a0-pure.cl
…
m04400_a1-optimized.cl
…
m04400_a1-pure.cl
…
m04400_a3-optimized.cl
…
m04400_a3-pure.cl
…
m04500_a0-optimized.cl
…
m04500_a0-pure.cl
…
m04500_a1-optimized.cl
…
m04500_a1-pure.cl
…
m04500_a3-optimized.cl
…
m04500_a3-pure.cl
…
m04510_a0-optimized.cl
…
m04510_a0-pure.cl
…
m04510_a1-optimized.cl
…
m04510_a1-pure.cl
…
m04510_a3-optimized.cl
…
m04510_a3-pure.cl
…
m04520_a0-optimized.cl
…
m04520_a0-pure.cl
…
m04520_a1-optimized.cl
…
m04520_a1-pure.cl
…
m04520_a3-optimized.cl
…
m04520_a3-pure.cl
…
m04700_a0-optimized.cl
…
m04700_a0-pure.cl
…
m04700_a1-optimized.cl
…
m04700_a1-pure.cl
…
m04700_a3-optimized.cl
…
m04700_a3-pure.cl
…
m04710_a0-optimized.cl
…
m04710_a0-pure.cl
…
m04710_a1-optimized.cl
…
m04710_a1-pure.cl
…
m04710_a3-optimized.cl
…
m04710_a3-pure.cl
…
m04800_a0-optimized.cl
…
m04800_a0-pure.cl
…
m04800_a1-optimized.cl
…
m04800_a1-pure.cl
…
m04800_a3-optimized.cl
…
m04800_a3-pure.cl
…
m04900_a0-optimized.cl
…
m04900_a0-pure.cl
…
m04900_a1-optimized.cl
…
m04900_a1-pure.cl
…
m04900_a3-optimized.cl
…
m04900_a3-pure.cl
…
m05000_a0-optimized.cl
…
m05000_a0-pure.cl
…
m05000_a1-optimized.cl
…
m05000_a1-pure.cl
…
m05000_a3-optimized.cl
…
m05000_a3-pure.cl
…
m05100_a0-optimized.cl
…
m05100_a0-pure.cl
…
m05100_a1-optimized.cl
…
m05100_a1-pure.cl
…
m05100_a3-optimized.cl
…
m05100_a3-pure.cl
…
m05200-pure.cl
…
m05300_a0-optimized.cl
…
m05300_a0-pure.cl
…
m05300_a1-optimized.cl
…
m05300_a1-pure.cl
…
m05300_a3-optimized.cl
…
m05300_a3-pure.cl
…
m05400_a0-optimized.cl
…
m05400_a0-pure.cl
…
m05400_a1-optimized.cl
…
m05400_a1-pure.cl
…
m05400_a3-optimized.cl
…
m05400_a3-pure.cl
…
m05500_a0-optimized.cl
…
m05500_a0-pure.cl
…
m05500_a1-optimized.cl
…
m05500_a1-pure.cl
…
m05500_a3-optimized.cl
…
m05500_a3-pure.cl
…
m05600_a0-optimized.cl
…
m05600_a0-pure.cl
…
m05600_a1-optimized.cl
…
m05600_a1-pure.cl
…
m05600_a3-optimized.cl
…
m05600_a3-pure.cl
…
m05800-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m05800-pure.cl
…
m06000_a0-optimized.cl
…
m06000_a0-pure.cl
…
m06000_a1-optimized.cl
…
m06000_a1-pure.cl
…
m06000_a3-optimized.cl
…
m06000_a3-pure.cl
…
m06100_a0-optimized.cl
…
m06100_a0-pure.cl
…
m06100_a1-optimized.cl
…
m06100_a1-pure.cl
…
m06100_a3-optimized.cl
…
m06100_a3-pure.cl
…
m06211-pure.cl
…
m06212-pure.cl
…
m06213-pure.cl
…
m06221-pure.cl
…
m06222-pure.cl
…
m06223-pure.cl
…
m06231-pure.cl
…
m06232-pure.cl
…
m06233-pure.cl
…
m06300-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m06300-pure.cl
…
m06400-pure.cl
…
m06500-pure.cl
…
m06600-pure.cl
…
m06700-pure.cl
…
m06800-pure.cl
…
m06900_a0-optimized.cl
…
m06900_a1-optimized.cl
…
m06900_a3-optimized.cl
…
m07000_a0-optimized.cl
…
m07000_a0-pure.cl
…
m07000_a1-optimized.cl
…
m07000_a1-pure.cl
…
m07000_a3-optimized.cl
…
m07000_a3-pure.cl
…
m07100-pure.cl
…
m07300_a0-optimized.cl
…
m07300_a0-pure.cl
…
m07300_a1-optimized.cl
…
m07300_a1-pure.cl
…
m07300_a3-optimized.cl
…
m07300_a3-pure.cl
…
m07400-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m07400-pure.cl
…
m07500_a0-optimized.cl
…
m07500_a0-pure.cl
…
m07500_a1-optimized.cl
…
m07500_a1-pure.cl
…
m07500_a3-optimized.cl
…
m07500_a3-pure.cl
…
m07700_a0-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07700_a1-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07700_a3-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a0-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a1-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07701_a3-optimized.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m07800_a0-optimized.cl
…
m07800_a1-optimized.cl
…
m07800_a3-optimized.cl
…
m07801_a0-optimized.cl
…
m07801_a1-optimized.cl
…
m07801_a3-optimized.cl
…
m07900-pure.cl
…
m08000_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08000_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08000_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m08100_a0-optimized.cl
…
m08100_a0-pure.cl
…
m08100_a1-optimized.cl
…
m08100_a1-pure.cl
…
m08100_a3-optimized.cl
…
m08100_a3-pure.cl
…
m08200-pure.cl
…
m08300_a0-optimized.cl
…
m08300_a0-pure.cl
…
m08300_a1-optimized.cl
…
m08300_a1-pure.cl
…
m08300_a3-optimized.cl
…
m08300_a3-pure.cl
…
m08400_a0-optimized.cl
…
m08400_a0-pure.cl
…
m08400_a1-optimized.cl
…
m08400_a1-pure.cl
…
m08400_a3-optimized.cl
…
m08400_a3-pure.cl
…
m08500_a0-pure.cl
…
m08500_a1-pure.cl
…
m08500_a3-pure.cl
…
m08600_a0-pure.cl
…
m08600_a1-pure.cl
…
m08600_a3-pure.cl
…
m08700_a0-optimized.cl
…
m08700_a1-optimized.cl
…
m08700_a3-optimized.cl
…
m08800-pure.cl
…
m08900-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m09000-pure.cl
Password Safe v2: Backport optimizations reducing bank conflicts in bcrypt
2021-07-26 10:17:21 +02:00
m09100-pure.cl
…
m09400-pure.cl
…
m09500-pure.cl
…
m09600-pure.cl
…
m09700_a0-optimized.cl
…
m09700_a1-optimized.cl
…
m09700_a3-optimized.cl
…
m09710_a0-optimized.cl
…
m09710_a1-optimized.cl
…
m09710_a3-optimized.cl
…
m09720_a0-optimized.cl
…
m09720_a1-optimized.cl
…
m09720_a3-optimized.cl
…
m09800_a0-optimized.cl
…
m09800_a1-optimized.cl
…
m09800_a3-optimized.cl
…
m09810_a0-optimized.cl
…
m09810_a1-optimized.cl
…
m09810_a3-optimized.cl
…
m09820_a0-optimized.cl
…
m09820_a1-optimized.cl
…
m09820_a3-optimized.cl
…
m09900_a0-optimized.cl
…
m09900_a0-pure.cl
…
m09900_a1-optimized.cl
…
m09900_a1-pure.cl
…
m09900_a3-optimized.cl
…
m09900_a3-pure.cl
…
m10100_a0-optimized.cl
…
m10100_a1-optimized.cl
…
m10100_a3-optimized.cl
…
m10300-pure.cl
…
m10400_a0-optimized.cl
…
m10400_a1-optimized.cl
…
m10400_a3-optimized.cl
…
m10410_a0-optimized.cl
…
m10410_a1-optimized.cl
…
m10410_a3-optimized.cl
…
m10420_a0-optimized.cl
…
m10420_a1-optimized.cl
…
m10420_a3-optimized.cl
…
m10500-pure.cl
…
m10700-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m10700-pure.cl
…
m10800_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a0-pure.cl
…
m10800_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a1-pure.cl
…
m10800_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m10800_a3-pure.cl
…
m10810_a0-optimized.cl
…
m10810_a0-pure.cl
…
m10810_a1-optimized.cl
…
m10810_a1-pure.cl
…
m10810_a3-optimized.cl
…
m10810_a3-pure.cl
…
m10820_a0-optimized.cl
…
m10820_a0-pure.cl
…
m10820_a1-optimized.cl
…
m10820_a1-pure.cl
…
m10820_a3-optimized.cl
…
m10820_a3-pure.cl
…
m10830_a0-optimized.cl
…
m10830_a0-pure.cl
…
m10830_a1-optimized.cl
…
m10830_a1-pure.cl
…
m10830_a3-optimized.cl
…
m10830_a3-pure.cl
…
m10840_a0-optimized.cl
…
m10840_a0-pure.cl
…
m10840_a1-optimized.cl
…
m10840_a1-pure.cl
…
m10840_a3-optimized.cl
…
m10840_a3-pure.cl
…
m10870_a0-optimized.cl
…
m10870_a0-pure.cl
…
m10870_a1-optimized.cl
…
m10870_a1-pure.cl
…
m10870_a3-optimized.cl
…
m10870_a3-pure.cl
…
m10900-pure.cl
…
m11000_a0-optimized.cl
…
m11000_a0-pure.cl
…
m11000_a1-optimized.cl
…
m11000_a1-pure.cl
…
m11000_a3-optimized.cl
…
m11000_a3-pure.cl
…
m11100_a0-optimized.cl
…
m11100_a0-pure.cl
…
m11100_a1-optimized.cl
…
m11100_a1-pure.cl
…
m11100_a3-optimized.cl
…
m11100_a3-pure.cl
…
m11200_a0-optimized.cl
…
m11200_a0-pure.cl
…
m11200_a1-optimized.cl
…
m11200_a1-pure.cl
…
m11200_a3-optimized.cl
…
m11200_a3-pure.cl
…
m11300-pure.cl
…
m11400_a0-pure.cl
…
m11400_a1-pure.cl
…
m11400_a3-pure.cl
…
m11500_a0-optimized.cl
…
m11500_a1-optimized.cl
…
m11500_a3-optimized.cl
…
m11600-optimized.cl
…
m11600-pure.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m11700_a0-optimized.cl
…
m11700_a0-pure.cl
…
m11700_a1-optimized.cl
…
m11700_a1-pure.cl
…
m11700_a3-optimized.cl
…
m11700_a3-pure.cl
…
m11750_a0-pure.cl
…
m11750_a1-pure.cl
…
m11750_a3-pure.cl
…
m11760_a0-pure.cl
…
m11760_a1-pure.cl
…
m11760_a3-pure.cl
…
m11800_a0-optimized.cl
…
m11800_a0-pure.cl
…
m11800_a1-optimized.cl
…
m11800_a1-pure.cl
…
m11800_a3-optimized.cl
…
m11800_a3-pure.cl
…
m11850_a0-pure.cl
…
m11850_a1-pure.cl
…
m11850_a3-pure.cl
…
m11860_a0-pure.cl
…
m11860_a1-pure.cl
…
m11860_a3-pure.cl
…
m11900-pure.cl
…
m12000-pure.cl
…
m12200-pure.cl
…
m12300-pure.cl
…
m12400-pure.cl
…
m12500-optimized.cl
…
m12500-pure.cl
Fix self-test functionality if FIXED_LOCAL_SIZE_COMP is used
2021-08-02 12:00:17 +02:00
m12600_a0-optimized.cl
…
m12600_a0-pure.cl
…
m12600_a1-optimized.cl
…
m12600_a1-pure.cl
…
m12600_a3-optimized.cl
…
m12600_a3-pure.cl
…
m12700-pure.cl
…
m12800-pure.cl
…
m12900-pure.cl
…
m13000-pure.cl
…
m13100_a0-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a0-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a1-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a1-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a3-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13100_a3-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m13200-pure.cl
…
m13300_a0-optimized.cl
…
m13300_a0-pure.cl
…
m13300_a1-optimized.cl
…
m13300_a1-pure.cl
…
m13300_a3-optimized.cl
…
m13300_a3-pure.cl
…
m13400-pure.cl
KeePass: Increase supported size for KeePass 1 databases from 300kB to 16MB
2021-06-30 13:16:03 +02:00
m13500_a0-optimized.cl
…
m13500_a0-pure.cl
…
m13500_a1-optimized.cl
…
m13500_a1-pure.cl
…
m13500_a3-optimized.cl
…
m13500_a3-pure.cl
…
m13600-pure.cl
fix buffer sizes for -m 13600 = WinZip
2021-07-30 15:23:33 +02:00
m13711-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13712-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13713-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13721-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13722-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13723-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13731-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13732-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13733-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13751-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13752-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13753-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13771-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13772-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13773-pure.cl
Improve PIM fix for use on macOS
2021-07-20 15:10:49 +02:00
m13800_a0-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a0-pure.cl
…
m13800_a1-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a1-pure.cl
…
m13800_a3-optimized.cl
AMD GPUs: Add inline assembly code for md5crypt/sha256crypt, PDF 1.7, 7-Zip, RAR3, Samsung Android and Windows Phone 8+
2021-07-26 07:59:12 +02:00
m13800_a3-pure.cl
…
m13900_a0-optimized.cl
…
m13900_a0-pure.cl
…
m13900_a1-optimized.cl
…
m13900_a1-pure.cl
…
m13900_a3-optimized.cl
…
m13900_a3-pure.cl
…
m14000_a0-pure.cl
…
m14000_a1-pure.cl
…
m14000_a3-pure.cl
Update large switch() cases in inc_common.cl and some inline assembly common functions for devices managed with HIP backend
2021-07-14 17:06:20 +02:00
m14100_a0-pure.cl
…
m14100_a1-pure.cl
…
m14100_a3-pure.cl
…
m14400_a0-optimized.cl
…
m14400_a0-pure.cl
…
m14400_a1-optimized.cl
…
m14400_a1-pure.cl
…
m14400_a3-optimized.cl
…
m14400_a3-pure.cl
…
m14511_a0-pure.cl
…
m14511_a1-pure.cl
…
m14511_a3-pure.cl
…
m14512_a0-pure.cl
…
m14512_a1-pure.cl
…
m14512_a3-pure.cl
…
m14513_a0-pure.cl
…
m14513_a1-pure.cl
…
m14513_a3-pure.cl
…
m14521_a0-pure.cl
…
m14521_a1-pure.cl
…
m14521_a3-pure.cl
…
m14522_a0-pure.cl
…
m14522_a1-pure.cl
…
m14522_a3-pure.cl
…
m14523_a0-pure.cl
…
m14523_a1-pure.cl
…
m14523_a3-pure.cl
…
m14531_a0-pure.cl
…
m14531_a1-pure.cl
…
m14531_a3-pure.cl
…
m14532_a0-pure.cl
…
m14532_a1-pure.cl
…
m14532_a3-pure.cl
…
m14533_a0-pure.cl
…
m14533_a1-pure.cl
…
m14533_a3-pure.cl
…
m14541_a0-pure.cl
…
m14541_a1-pure.cl
…
m14541_a3-pure.cl
…
m14542_a0-pure.cl
…
m14542_a1-pure.cl
…
m14542_a3-pure.cl
…
m14543_a0-pure.cl
…
m14543_a1-pure.cl
…
m14543_a3-pure.cl
…
m14551_a0-pure.cl
…
m14551_a1-pure.cl
…
m14551_a3-pure.cl
…
m14552_a0-pure.cl
…
m14552_a1-pure.cl
…
m14552_a3-pure.cl
…
m14553_a0-pure.cl
…
m14553_a1-pure.cl
…
m14553_a3-pure.cl
…
m14611-pure.cl
…
m14612-pure.cl
…
m14613-pure.cl
…
m14621-pure.cl
…
m14622-pure.cl
…
m14623-pure.cl
…
m14631-pure.cl
…
m14632-pure.cl
…
m14633-pure.cl
…
m14641-pure.cl
…
m14642-pure.cl
…
m14643-pure.cl
…
m14700-pure.cl
…
m14800-pure.cl
…
m14900_a0-optimized.cl
…
m14900_a1-optimized.cl
…
m14900_a3-optimized.cl
…
m15000_a0-optimized.cl
…
m15000_a0-pure.cl
…
m15000_a1-optimized.cl
…
m15000_a1-pure.cl
…
m15000_a3-optimized.cl
…
m15000_a3-pure.cl
…
m15100-pure.cl
…
m15300-pure.cl
…
m15400_a0-optimized.cl
…
m15400_a1-optimized.cl
…
m15400_a3-optimized.cl
…
m15500_a0-optimized.cl
…
m15500_a0-pure.cl
…
m15500_a1-optimized.cl
…
m15500_a1-pure.cl
…
m15500_a3-optimized.cl
…
m15500_a3-pure.cl
…
m15600-pure.cl
…
m15700-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m15900-pure.cl
…
m16000_a0-pure.cl
…
m16000_a1-pure.cl
…
m16000_a3-pure.cl
…
m16100_a0-optimized.cl
…
m16100_a0-pure.cl
…
m16100_a1-optimized.cl
…
m16100_a1-pure.cl
…
m16100_a3-optimized.cl
…
m16100_a3-pure.cl
…
m16200-pure.cl
…
m16300-pure.cl
…
m16400_a0-optimized.cl
…
m16400_a0-pure.cl
…
m16400_a1-optimized.cl
…
m16400_a1-pure.cl
…
m16400_a3-optimized.cl
…
m16400_a3-pure.cl
…
m16511_a0-pure.cl
…
m16511_a1-pure.cl
…
m16511_a3-pure.cl
…
m16512_a0-pure.cl
…
m16512_a1-pure.cl
…
m16512_a3-pure.cl
…
m16513_a0-pure.cl
…
m16513_a1-pure.cl
…
m16513_a3-pure.cl
…
m16600_a0-optimized.cl
…
m16600_a0-pure.cl
…
m16600_a1-optimized.cl
…
m16600_a1-pure.cl
…
m16600_a3-optimized.cl
…
m16600_a3-pure.cl
…
m16800-pure.cl
WPA Kernels: Increased performance by 3.5% for backend devices controlled by CUDA backend
2021-07-04 12:24:55 +02:00
m16801-pure.cl
…
m16900-pure.cl
…
m17200_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17200_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17200_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17210_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17220_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17225_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a0-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a1-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17230_a3-pure.cl
Fix address space of crc32tab[] in -m 172xx
2021-07-12 08:56:10 +02:00
m17300_a0-optimized.cl
…
m17300_a1-optimized.cl
…
m17300_a3-optimized.cl
…
m17400_a0-optimized.cl
…
m17400_a1-optimized.cl
…
m17400_a3-optimized.cl
…
m17500_a0-optimized.cl
…
m17500_a1-optimized.cl
…
m17500_a3-optimized.cl
…
m17600_a0-optimized.cl
…
m17600_a1-optimized.cl
…
m17600_a3-optimized.cl
…
m17700_a0-optimized.cl
…
m17700_a1-optimized.cl
…
m17700_a3-optimized.cl
…
m17800_a0-optimized.cl
…
m17800_a1-optimized.cl
…
m17800_a3-optimized.cl
…
m17900_a0-optimized.cl
…
m17900_a1-optimized.cl
…
m17900_a3-optimized.cl
…
m18000_a0-optimized.cl
…
m18000_a1-optimized.cl
…
m18000_a3-optimized.cl
…
m18100_a0-pure.cl
…
m18100_a1-pure.cl
…
m18100_a3-pure.cl
…
m18200_a0-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a0-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a1-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a1-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a3-optimized.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18200_a3-pure.cl
Add rc4_next_16_global() and fix address space of edata buffer in -m 13100 and -m18200
2021-06-23 08:36:17 +02:00
m18300-pure.cl
…
m18400-pure.cl
…
m18500_a0-pure.cl
…
m18500_a1-pure.cl
…
m18500_a3-pure.cl
…
m18600-pure.cl
Blowfish Kernels: Backport optimizations reducing bank conflicts from bcrypt to Password Safe v2 and Open Document Format (ODF) 1.1
2021-07-26 13:38:39 +02:00
m18700_a0-optimized.cl
…
m18700_a0-pure.cl
…
m18700_a1-optimized.cl
…
m18700_a1-pure.cl
…
m18700_a3-optimized.cl
…
m18700_a3-pure.cl
…
m18800-pure.cl
…
m18900-pure.cl
…
m19000-pure.cl
…
m19100-pure.cl
…
m19200-pure.cl
…
m19300_a0-pure.cl
…
m19300_a1-pure.cl
…
m19300_a3-pure.cl
…
m19500_a0-pure.cl
…
m19500_a1-pure.cl
…
m19500_a3-pure.cl
…
m19600-pure.cl
Fix variable declaration block level in -m 19600 and -m 19700
2021-07-13 22:22:53 +02:00
m19700-pure.cl
Fix variable declaration block level in -m 19600 and -m 19700
2021-07-13 22:22:53 +02:00
m19800-pure.cl
…
m19900-pure.cl
…
m20011-pure.cl
…
m20012-pure.cl
…
m20013-pure.cl
…
m20500_a0-pure.cl
…
m20500_a1-pure.cl
…
m20500_a3-pure.cl
…
m20510_a0-pure.cl
…
m20510_a1-pure.cl
…
m20510_a3-pure.cl
…
m20600-pure.cl
…
m20710_a0-optimized.cl
…
m20710_a0-pure.cl
…
m20710_a1-optimized.cl
…
m20710_a1-pure.cl
…
m20710_a3-optimized.cl
…
m20710_a3-pure.cl
…
m20720_a0-pure.cl
…
m20720_a1-pure.cl
…
m20720_a3-pure.cl
…
m20800_a0-optimized.cl
…
m20800_a0-pure.cl
…
m20800_a1-optimized.cl
…
m20800_a1-pure.cl
…
m20800_a3-optimized.cl
…
m20800_a3-pure.cl
…
m20900_a0-optimized.cl
…
m20900_a0-pure.cl
…
m20900_a1-optimized.cl
…
m20900_a1-pure.cl
…
m20900_a3-optimized.cl
…
m20900_a3-pure.cl
…
m21000_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a0-pure.cl
…
m21000_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a1-pure.cl
…
m21000_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m21000_a3-pure.cl
…
m21100_a0-optimized.cl
…
m21100_a0-pure.cl
…
m21100_a1-optimized.cl
…
m21100_a1-pure.cl
…
m21100_a3-optimized.cl
…
m21100_a3-pure.cl
…
m21200_a0-optimized.cl
…
m21200_a0-pure.cl
…
m21200_a1-optimized.cl
…
m21200_a1-pure.cl
…
m21200_a3-optimized.cl
…
m21200_a3-pure.cl
…
m21300_a0-pure.cl
…
m21300_a1-pure.cl
…
m21300_a3-pure.cl
…
m21400_a0-optimized.cl
…
m21400_a0-pure.cl
…
m21400_a1-optimized.cl
…
m21400_a1-pure.cl
…
m21400_a3-optimized.cl
…
m21400_a3-pure.cl
…
m21500-pure.cl
…
m21600-pure.cl
…
m21700-pure.cl
…
m21800-pure.cl
…
m22000-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m22001-pure.cl
More CUDA special backports to HIP
2021-07-18 22:56:22 +02:00
m22100-pure.cl
…
m22200_a0-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a0-pure.cl
…
m22200_a1-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a1-pure.cl
…
m22200_a3-optimized.cl
Backport more ROCm based optimizations to HIP
2021-07-15 23:34:27 +02:00
m22200_a3-pure.cl
…
m22300_a0-optimized.cl
…
m22300_a0-pure.cl
…
m22300_a1-optimized.cl
…
m22300_a1-pure.cl
…
m22300_a3-optimized.cl
…
m22300_a3-pure.cl
…
m22400-pure.cl
…
m22500_a0-optimized.cl
…
m22500_a0-pure.cl
…
m22500_a1-optimized.cl
…
m22500_a1-pure.cl
…
m22500_a3-optimized.cl
…
m22500_a3-pure.cl
…
m22600-pure.cl
…
m22700-pure.cl
HIP Backend: Added support to support HIP 4.4 and later, but added check to rule out older versions because they are incompatible
2021-07-23 16:04:34 +02:00
m22911_a0-pure.cl
…
m22911_a1-pure.cl
…
m22911_a3-pure.cl
…
m22921_a0-pure.cl
…
m22921_a1-pure.cl
…
m22921_a3-pure.cl
…
m22931_a0-pure.cl
…
m22931_a1-pure.cl
…
m22931_a3-pure.cl
…
m22941_a0-pure.cl
…
m22941_a1-pure.cl
…
m22941_a3-pure.cl
…
m22951_a0-pure.cl
…
m22951_a1-pure.cl
…
m22951_a3-pure.cl
…
m23001_a0-optimized.cl
…
m23001_a0-pure.cl
…
m23001_a1-optimized.cl
…
m23001_a1-pure.cl
…
m23001_a3-optimized.cl
…
m23001_a3-pure.cl
…
m23002_a0-optimized.cl
…
m23002_a0-pure.cl
…
m23002_a1-optimized.cl
…
m23002_a1-pure.cl
…
m23002_a3-optimized.cl
…
m23002_a3-pure.cl
…
m23003_a0-optimized.cl
…
m23003_a0-pure.cl
…
m23003_a1-optimized.cl
…
m23003_a1-pure.cl
…
m23003_a3-optimized.cl
…
m23003_a3-pure.cl
…
m23100-pure.cl
…
m23200-pure.cl
…
m23300-pure.cl
…
m23400-pure.cl
…
m23500-pure.cl
…
m23600-pure.cl
…
m23700-optimized.cl
…
m23700-pure.cl
Fix self-test functionality if FIXED_LOCAL_SIZE_COMP is used
2021-08-02 12:00:17 +02:00
m23800-optimized.cl
…
m23800-pure.cl
Fix self-test functionality if FIXED_LOCAL_SIZE_COMP is used
2021-08-02 12:00:17 +02:00
m23900-pure.cl
…
m24100-pure.cl
…
m24200-pure.cl
…
m24300_a0-optimized.cl
…
m24300_a0-pure.cl
…
m24300_a1-optimized.cl
…
m24300_a1-pure.cl
…
m24300_a3-optimized.cl
…
m24300_a3-pure.cl
…
m24410-pure.cl
…
m24420-pure.cl
…
m24500-pure.cl
…
m24610-pure.cl
…
m24620-pure.cl
…
m24630-pure.cl
…
m24700_a0-optimized.cl
…
m24700_a0-pure.cl
…
m24700_a1-optimized.cl
…
m24700_a1-pure.cl
…
m24700_a3-optimized.cl
…
m24700_a3-pure.cl
…
m24800_a0-optimized.cl
…
m24800_a0-pure.cl
…
m24800_a1-optimized.cl
…
m24800_a1-pure.cl
…
m24800_a3-optimized.cl
…
m24800_a3-pure.cl
…
m24900_a0-optimized.cl
…
m24900_a1-optimized.cl
…
m24900_a3-optimized.cl
…
m25000-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m25100-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m25200-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m25300-pure.cl
…
m25400-pure.cl
…
m25500-pure.cl
…
m25600-pure.cl
Fix password address space in m25600_init kernel
2021-07-07 10:35:41 +02:00
m25700_a0-optimized.cl
…
m25700_a1-optimized.cl
…
m25700_a3-optimized.cl
Added some HIP version checks, fall back to OpenCL automatically
2021-08-04 20:49:22 +02:00
m25800-pure.cl
Bcrypt-SHA1/MD5 Kernels: Get rid of local memory use for binary to hex conversion to avoid false negatives on several OpenCL runtimes
2021-07-06 12:53:38 +02:00
m25900-pure.cl
…
m26000_a0-pure.cl
…
m26000_a1-pure.cl
…
m26000_a3-pure.cl
…
m26100-pure.cl
…
m26200_a0-pure.cl
…
m26200_a1-pure.cl
…
m26200_a3-pure.cl
…
m26300_a0-pure.cl
…
m26300_a1-pure.cl
…
m26300_a3-pure.cl
…
m26401_a0-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26401_a1-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26401_a3-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26402_a0-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26402_a1-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26402_a3-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26403_a0-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26403_a1-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26403_a3-optimized.cl
Added hash-mode: AES-128/192/256-ECB NOKDF
2021-06-26 17:12:10 +02:00
m26500-pure.cl
Added hash-mode: iPhone passcode (UID key + System Keybag)
2021-07-03 19:03:06 +02:00
m26600-pure.cl
add min/max data length limits to MetaMask Wallet
2021-07-04 20:14:25 +02:00
m26700-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m26800-pure.cl
with SNMPv3, follow optimized logic path with pw_len <= 64, update changes/readme entries
2021-08-03 22:02:50 +02:00
m26900-pure.cl
reduced the amount of memory allocated in gpu for SNMPv3 HMAC-SHA384-256
2021-08-03 21:29:07 +02:00
m27000-pure.cl
rename to 27300, reduced the amount of memory allocated in gpu for SNMPv3 HMAC-SHA512-384
2021-08-03 21:42:42 +02:00
m27100-pure.cl
Expect Hex input, removed OPTS_TYPE_PT_ALWAYS_HEXIFY, added benchmark mask.
2021-08-02 11:40:14 +02:00
m27300-pure.cl
rename to 27300, reduced the amount of memory allocated in gpu for SNMPv3 HMAC-SHA512-384
2021-08-03 21:42:42 +02:00
markov_be.cl
…
markov_le.cl
…
shared.cl
Implement gpu_bzero
2021-07-17 19:00:10 +03:00